7 digital interface formats – Cirrus Logic CS43L22 User Manual
Page 30
30
DS792F2
CS43L22
Confidential Draft
3/4/10
Note:
*The marked sample rate values are not exact representations of the actual frame clock frequency
They have been truncated to 4 decimal places. The exact value can be calculated by dividing the
MCLK being used by the desired MCLK/LRCK ratio.
Table 1. Serial Port Clocking
4.7
Digital Interface Formats
The serial port operates in standard I²S, Left-Justified, Right-Justified, or DSP Mode digital interface formats
with varying bit depths from 16 to 24. Data is clocked into the DAC on the rising edge of SCLK.
27.0000
8.0000
11
1
1
01
0
12.0000
11
0
1
01
0
24.0000
10
0
1
01
0
32.0000
01
1
1
01
0
*44.1176...
01
0
1
11
0
48.0000
01
0
1
01
0
*11.0294...
11
0
1
11
0
*22.0588...
10
0
1
11
0
16.0000
10
1
1
01
0
MCLK
(MHz)
Sample Rate,
Fs (kHz)
SPEED[1:0]
(AUTO=’0’b)
32kGROUP
VIDEOCLK
RATIO[1:0]
MCLKDIV2
LRCK
SCLK
M S B
L S B
M S B
L S B
AOUTA
L e ft C h a n n e l
R i g h t C h a n n e l
SDIN
AOUTB
MSB
Figure 12. I²S Format
LRCK
SCLK
MSB
LSB
MSB
LSB
Left Channel
Right Channel
SDIN
MSB
AOUTA
AOUTB
Figure 13. Left-Justified Format
LR C K
SC LK
M S B
L S B
M S B
L S B
L e f t C h a n n e l
R i g h t C h a n n e l
SD IN
AO U TA
AO U TB
Audio W ord Length (AW L)
Figure 14. Right-Justified Format\