Document Outline

• Table of Contents
• List of Figures
• 1. Pin Descriptions
  • 1.1 I/O Pin Characteristics
• 2. Typical Connection Diagram
• 3. Characteristic and Specifications
• 4. Applications
  • 4.1 Overview
    • 4.1.1 Basic Architecture
    • 4.1.2 Line Inputs
    • 4.1.3 Line & Headphone Outputs
    • 4.1.4 Speaker Driver Outputs
    • 4.1.5 Fixed Function DSP Engine
    • 4.1.6 Beep Generator
    • 4.1.7 Power Management
  • 4.2 DSP Engine
    • 4.2.1 Beep Generator
    • 4.2.2 Limiter
  • 4.3 Analog Passthrough
  • 4.4 Analog Outputs
  • 4.5 PWM Outputs
    • 4.5.1 Mono Speaker Output Configuration
    • 4.5.2 VP Battery Compensation
  • 4.6 Serial Port Clocking
  • 4.7 Digital Interface Formats
    • 4.7.1 DSP Mode
  • 4.8 Initialization
  • 4.9 Recommended Power-Up Sequence
  • 4.10 Recommended Power-Down Sequence
  • 4.11 Required Initialization Settings
• 5. Control Port Operation
  • 5.1 I·C Control
    • 5.1.1 Memory Address Pointer (MAP)
• 6. Register Quick Reference
• 7. Register Description
  • 7.1 Chip I.D. and Revision Register (Address 01h) (Read Only)
    • 7.1.1 Chip I.D. (Read Only)
    • 7.1.2 Chip Revision (Read Only)
  • 7.2 Power Control 1 (Address 02h)
    • 7.2.1 Power Down
  • 7.3 Power Control 2 (Address 04h)
    • 7.3.1 Headphone Power Control
    • 7.3.2 Speaker Power Control
  • 7.4 Clocking Control (Address 05h)
    • 7.4.1 Auto-Detect
    • 7.4.2 Speed Mode
    • 7.4.3 32kHz Sample Rate Group
    • 7.4.4 27 MHz Video Clock
    • 7.4.5 Internal MCLK/LRCK Ratio
    • 7.4.6 MCLK Divide By 2
  • 7.5 Interface Control 1 (Address 06h)
    • 7.5.1 Master/Slave Mode
    • 7.5.2 SCLK Polarity
    • 7.5.3 DSP Mode
    • 7.5.4 DAC Interface Format
    • 7.5.5 Audio Word Length
  • 7.6 Interface Control 2 (Address 07h)
    • 7.6.1 SCLK equals MCLK
    • 7.6.2 Speaker/Headphone Switch Invert
  • 7.7 Passthrough x Select: PassA (Address 08h), PassB (Address 09h)
    • 7.7.1 Passthrough Input Channel Mapping
  • 7.8 Analog ZC and SR Settings (Address 0Ah)
    • 7.8.1 Ch. x Analog Soft Ramp
    • 7.8.2 Ch. x Analog Zero Cross
  • 7.9 Passthrough Gang Control (Address 0Ch)
    • 7.9.1 Passthrough Channel B=A Gang Control
  • 7.10 Playback Control 1 (Address 0Dh)
    • 7.10.1 Headphone Analog Gain
    • 7.10.2 Playback Volume Setting B=A
    • 7.10.3 Invert PCM Signal Polarity
    • 7.10.4 Master Playback Mute
  • 7.11 Miscellaneous Controls (Address 0Eh)
    • 7.11.1 Passthrough Analog
    • 7.11.2 Passthrough Mute
    • 7.11.3 Freeze Registers
    • 7.11.4 HP/Speaker De-Emphasis
    • 7.11.5 Digital Soft Ramp
    • 7.11.6 Digital Zero Cross
  • 7.12 Playback Control 2 (Address 0Fh)
    • 7.12.1 Headphone Mute
    • 7.12.2 Speaker Mute
    • 7.12.3 Speaker Volume Setting B=A
    • 7.12.4 Speaker Channel Swap
    • 7.12.5 Speaker MONO Control
    • 7.12.6 Speaker Mute 50/50 Control
  • 7.13 Passthrough x Volume: PASSAVOL (Address 14h) & PASSBVOL (Address 15h)
    • 7.13.1 Passthrough x Volume
  • 7.14 PCMx Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh)
    • 7.14.1 PCM Channel x Mute
    • 7.14.2 PCM Channel x Volume
  • 7.15 Beep Frequency & On Time (Address 1Ch)
    • 7.15.1 Beep Frequency
    • 7.15.2 Beep On Time
  • 7.16 Beep Volume & Off Time (Address 1Dh)
    • 7.16.1 Beep Off Time
    • 7.16.2 Beep Volume
  • 7.17 Beep & Tone Configuration (Address 1Eh)
    • 7.17.1 Beep Configuration
    • 7.17.2 Beep Mix Disable
    • 7.17.3 Treble Corner Frequency
    • 7.17.4 Bass Corner Frequency
    • 7.17.5 Tone Control Enable
  • 7.18 Tone Control (Address 1Fh)
    • 7.18.1 Treble Gain
    • 7.18.2 Bass Gain
  • 7.19 Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)
    • 7.19.1 Master Volume Control
  • 7.20 Headphone Volume Control: HPA (Address 22h) & HPB (Address 23h)
    • 7.20.1 Headphone Volume Control
  • 7.21 Speaker Volume Control: SPKA (Address 24h) & SPKB (Address 25h)
    • 7.21.1 Speaker Volume Control
  • 7.22 PCM Channel Swap (Address 26h)
    • 7.22.1 PCM Channel Swap
  • 7.23 Limiter Control 1, Min/Max Thresholds (Address 27h)
    • 7.23.1 Limiter Maximum Threshold
    • 7.23.2 Limiter Cushion Threshold
    • 7.23.3 Limiter Soft Ramp Disable
    • 7.23.4 Limiter Zero Cross Disable
  • 7.24 Limiter Control 2, Release Rate (Address 28h)
    • 7.24.1 Peak Detect and Limiter
    • 7.24.2 Peak Signal Limit All Channels
    • 7.24.3 Limiter Release Rate
  • 7.25 Limiter Attack Rate (Address 29h)
    • 7.25.1 Limiter Attack Rate
  • 7.26 Status (Address 2Eh) (Read Only)
    • 7.26.1 Serial Port Clock Error (Read Only)
    • 7.26.2 DSP Engine Overflow (Read Only)
    • 7.26.3 PCMx Overflow (Read Only)
  • 7.27 Battery Compensation (Address 2Fh)
    • 7.27.1 Battery Compensation
    • 7.27.2 VP Monitor
    • 7.27.3 VP Reference
  • 7.28 VP Battery Level (Address 30h) (Read Only)
    • 7.28.1 VP Voltage Level (Read Only)
  • 7.29 Speaker Status (Address 31h) (Read Only)
    • 7.29.1 Speaker Current Load Status (Read Only)
    • 7.29.2 SPKR/HP Pin Status (Read Only)
  • 7.30 Charge Pump Frequency (Address 34h)
    • 7.30.1 Charge Pump Frequency
• 8. Analog Performance Plots
  • 8.1 Headphone THD+N versus Output Power Plots
• 9. Example System Clock Frequencies
  • 9.1 Auto Detect Enabled
  • 9.2 Auto Detect Disabled
• 10. PCB Layout Considerations
  • 10.1 Power Supply, Grounding
  • 10.2 QFN Thermal Pad
• 11. Digital Filter Plots
• 12. Parameter Definitions
• 13. Package Dimensions
• 14. Ordering Information
• 15. References
• 16. Revision History