Cirrus Logic CS43L22 - Manual (Page 55)

DS792F2 55
CS43L22
Confidential Draft
3/4/10
7.25 Limiter Attack Rate (Address 29h)
7.25.1 Limiter Attack Rate
Sets the rate at which the limiter applies digital attenuation from levels above the MAX[2:0] threshold
(
“Limiter Maximum Threshold” on page 53 ).
Note: The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and
the DIGSFT ( “Digital Soft Ramp” on page 44 ) and DIGZC ( “Digital Zero Cross” on page 45 ) setting unless
the respective disable bit ( “Limiter Soft Ramp Disable” on page 53 or “Limiter Zero Cross Disable” on
page 54 ) is enabled.
7.26 Status (Address 2Eh) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
7.26.1 Serial Port Clock Error (Read Only)
Indicates the status of the MCLK to LRCK ratio.
Note: On initial power up and application of clocks, this bit will report ‘1’b as the serial port re-synchro-
nizes.
7.26.2 DSP Engine Overflow (Read Only)
Indicates the over-range status in the DSP data path.
7 6 5 4 3 2 1 0
Reserved Reserved LIMARATE5 LIMARATE4 LIMARATE3 LIMARATE2 LIMARATE1 LIMARATE0
LIMARATE[5:0] Attack Time
00 0000 Fastest Attack
··· ···
11 1111 Slowest Attack
Application: “Limiter” on page 22
7 6 5 4 3 2 1 0
Reserved SPCLKERR DSPAOVFL DSPBOVFL PCMAOVFL PCMBOVFL Reserved Reserved
SPCLKERR Serial Port Clock Status:
0 MCLK/LRCK ratio is valid.
1 MCLK/LRCK ratio is not valid.
Application: “Serial Port Clocking” on page 29
DSPxOVFL DSP Overflow Status:
0 No digital clipping has occurred in the data path after the DSP.
1 Digital clipping has occurred in the data path after the DSP.
Application: “DSP Engine” on page 21