Cirrus Logic CDB48500-USB - Manual (Page 21)

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3.1.11.2 Clock and Data Flow for S/PDIF Input
Figure 3-3. Simplified Clock and Data Flow for S/PDIF Input
Figure 3-3 illustrates the S/PDIF clocking architecture used when any S/PDIF RX is used as an audio source, as
described in Section 4.2.2, “Changing the Audio Input Source” on page 4-3 ). MCLK recovered from the
incoming S/PDIF stream is the MCLK for the system. The CS8416 also generates SCLK and LRCLK for the DAI
side of the DSP from the recovered MCLK.
On the output side, the CS485XX slaves to MCLK from CS8416 and masters SCLK and LRCLK for the DAC
side of the CS42448.
An example of this clocking scheme can be found in pcm.cpa.
CS42448
2x
CS485XX
CS42448
2x
CS8416
MUXED_DSP_SCLK1
DSP_SCLK
DSP_LRCLK
DSP
_
DA
I4
MUXED_DSP_LRCLK1
XT
AL_O
UT
S/PDIF Input
DSP_DA0[3:0]
XMTA SPDIF OUT
MUXED_MCLK
DAI
DAO
SDIN
SDOUT
PLL
SPDIF
Input
\S
PD
IF J100 J101
1
2
CH_
ADC
\O
N_BRD1
\O
N_BR
D2
HDR1
HD
R2
Use these jumper settings for the clocking
mode and inputs shown in diagram.