Cirrus Logic CS4955 - Manual (Page 18)

CS4954 CS4955
18 DS278F6
VSYNC stays low for 2.5 line-times and transitions
high with the beginning of line 315. Video input on
the V [7:0] pins is expected between line 336
through line 622.
5.2.7 Progressive Scan
The CS4954/5 supports a pseudo-progessive scan
mode for which “odd” and “even” numbered line
information is presented in “odd” numbered line
positions by varying the vertical blanking timing.
This preserves precise MPEG-2 frame rates of 30
and 25 frames per second. This mode is in contrast
to other digital video encoders, which commonly
support progressive scan by repetitively displaying
a 262 line field (524/525 lines for NTSC). The
common method is flawed: over time, the output
display rate will overrun a system-clock-locked
MPEG-2 decompressor and display a field twice
every 8.75 seconds.
5.2.8 NTSC Progressive Scan
VSYNC will transition low at line four to begin
field one and will remain low for three lines or
2574 pixel cycles (858 × 3). NTSC interlaced tim-
ing is illustrated in Figure
9 . In this mode, the
CS4954/5 expects digital video input at the V [7:0]
pins for 240 lines beginning on active video line 22
and continuing through line 261.
NTSC Vertical Timing (odd field)
Line
HSYNC
VSYNC
FIELD
3 4 5 6 7 8 9 10
NTSC Vertical Timing (even field)
PAL Vertical Timing (odd field)
PAL Vertical Timing (even field)
264 265 266 267 268 269 270 271
265 1 2 3 4 5 6 7
311 312 313 314 315 316 317 318
Line
HSYNC
VSYNC
FIELD
Line
HSYNC
VSYNC
FIELD
Line
HSYNC
VSYNC
FIELD
Figure 6. Vertical Timing