Cirrus Logic CS4955 - Manual (Page 23)

CS4954 CS4955
DS278F6 23
5.7 Subcarrier Compensation
Since the subcarrier is synthesized from CLK, the
subcarrier frequency error will track the clock fre-
quency error. If the input clock has a tolerance of
200 ppm then the resulting subcarrier will also
have a tolerance of 200 ppm. Per the NTSC speci-
fication, the final subcarrier tolerance is ±10 Hz
which is approximately 3 ppm. Care must be taken
in selecting a suitable clock source.
In MPEG-2 system environments the clock is actu-
ally recovered from the data stream. In these cases
the recovered clock can be 27 MHz
±50 ppm or
±1350 Hz. It varies per television, but in many cas-
es given an MPEG-2 system clock of 27 MHz,
±1350 Hz, the resultant color subcarrier produced
will be outside of the television’s ability to com-
pensate and the chrominance information will not
be displayed (resulting in a black-and-white picture
only).
The CS4954/5 is designed to provide automatic
compensation for an excessively inaccurate
MPEG-2 system clock. Sub-carrier compensation
is enabled through the XTAL bit of the
CONTROL_2 Register. When enabled, the
CS4954/5 will utilize a common quartz color burst
crystal (3.579545 MHz ± 50 ppm for NTSC) at-
tached to the XTAL_IN and XTAL_OUT pins to
automatically compare and compensate the color
subcarrier synthesis process.
5.8 Closed Caption Insertion
The CS4954/5 is capable of NTSC Closed Caption
insertion on lines 21 and 284 independently.
Closed captioning is enabled for either one or both
lines via the CC_EN [1:0] Register bits and the
data to be inserted is also written into the four
Closed Caption Data registers. The CS4954/5,
when enabled, automatically generates the seven
cycles of clock run-in (32 times the line rate), does
start bit insertion (001), and finally does insertion
of the two data bytes per line. Data low at the video
outputs corresponds to 0 IRE and data high corre-
sponds to 50 IRE.
There are two independent 8-bit registers per line
(CC_21_1 & CC_21_2 for line 21 and CC_284_1
& CC_284_2 for line 284). Interrupts are also pro-
vided to simplify the handshake between the driver
software and the device. Typically the host writes
System Fsubcarrier Value (hex)
NTSC-M, NTSC-J 3.5795455 MHz 43E0F83E
PAL-B, D, G, H, I, N 4.43361875 MHz 54131596
PAL-N (Argentina)
3.582056 MHz 43ED288D
PAL-M 3.579611 MHz 43CDDFC7
Table 3.
Address Register
NTSC-M
ITU
R.BT601
NTSC-J
ITU
R.BT601
NTSC-M
RS170A
PAL-
B,D,G,H,I PAL-M PAL-N
PAL-N
Comb.
(Argent)
0×00 CONTROL_0 01h 01h 21h 41h 61h A1h 81h
0×01 CONTROL_1 12h 10h 16h 30h 12h 30h 30h
0×04 CONTROL_4 07h 07h 07h 07h 07h 07h 07h
0×05 CONTROL_5 78h 78h 78h 78h 78h 78h 78h
0×10 SC_AMP 1Ch 1Ch 1Ch 15h 15h 15h 15h
0×11 SC_SYNTH0 3Eh 3Eh 3Eh 96h C7h 96h 8Ch
0×12 SC_SYNTH1 F8h F8h F8h 15h DFh 15h 28h
0×13 SC_SYNTH2 E0h E0h E0h 13h CDh 13h EDh
0×14 SC_SYNTH3 43h 43h 43h 54h 43h 54h 43h
Table 4. Multi-standard Format Register Configurations