Cirrus Logic CS5461A - Manual (Page 27)

CS5461A
DS661F3 27
iCPU Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
are sampled, the logic driven by CPUCLK should not be active during the sample edge.
0 = Normal operation (default)
1 = Minimize noise when CPUCLK is driving rising-edge logic
K[3:0] Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-
tween 1 and 16. A value of “0000” will set K to 16 (not zero). K = 1 at reset.
6.2 Current and Voltage DC Offset Register ( I
DCoff
,V
DCoff
)
Address: 1 (Current DC Offset); 3 (Voltage DC Offset)
Default = 0x000000
The DC Offset registers (I
DCoff
,V
DCoff
) are initialized to 0.0 on reset. When DC Offset calibration is performed, the
register is updated with the DC offset measured over a computation cycle. DRDY will be asserted at the end of
the calibration. This register may be read and stored for future system offset compensation. The value is repre-
sented in two's complement notation and in the range of -1.0
 I
DCoff
, V
DCoff
 1.0, with the binary point to the
right of the MSB.
6.3 Current and Voltage Gain Register ( I
gn
,V
gn
)
Address: 2 (Current Gain); 4 (Voltage Gain)
Default = 0x400000 = 1.000
The gain registers (I
gn
,V
gn
) are initialized to 1.0 on reset. When either a AC or DC Gain calibration is performed,
the register is updated with the gain measured over a computation cycle. DRDY will be asserted at the end of
the calibration. This register may be read and stored for future system gain compensation. The value is in the
range 0.0
 I
gn
,V
gn
< 3.9999, with the binary point to the right of the second MSB.
6.4 Cycle Count Register
Address: 5
Default = 0x000FA0 = 4000
Cycle Count, denoted as N, determines the length of one computation cycle. During continuous conversions,
the computation cycle frequency is (MCLK/K)/(1024
N). A one second computational cycle period occurs when
MCLK = 4.096 MHz, K = 1, and N = 4000.
MSB LSB
-(2 0 ) 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23
MSB LSB
2
1
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6 ..... 2
-16
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
MSB LSB
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16 ..... 2
6
2
5
2
4
2
3
2
2
2
1
2
0