Cirrus Logic CS61584A - Manual (Page 20)

CS61584A
20 DS261PP5
DS261PP5
6. REFERENCE CLOCK
The CS61584A requires a reference clock with a
minimum accuracy of ±100 ppm for T1 and E1 ap-
plications. This clock can be either a 1X clock (i.e.,
1.544 MHz or 2.048 MHz), or can be a 8X clock
(i.e., 12.352 MHz or 16.384 MHz) as selected by
the 1XCLK pin. This clock may be supplied from
internal system timing or a CMOS crystal oscillator
and input to the REFCLK pin. An 8X quartz crystal
may be connected across the REFCLK and XTA-
LOUT pins and the 1XCLK pin set low. The quartz
crystal and CMOS crystal oscillator specifications
and are presented in the Applications section.
In systems with a jittered transmit clock, the refer-
ence clock should not be tied to the transmit clock
and a separate external quartz crystal or crystal os-
cillator should drive the reference clock input. Any
jitter present on the reference clock will not be fil-
tered by the jitter attenuator.
7. POWER-UP RESET
On power-up, the device is held in a static state un-
til the power supply achieves approximately 60%
of the power supply voltage. When this threshold is
crossed, the device waits another 10 ms to allow the
power supply to reach operating voltage and then
calibrates the transmit and receive circuitry. This
initial calibration takes less than 20 ms but can oc-
cur only if REFCLK and TCLK are present.
Power-up reset initializes the control logic and reg-
ister set and performs the same functions as the RE-
SET pin. During Host mode operation, a reset event
is indicated by the Latched-Reset bit in the Status
register.
8. LINE CONTROL AND MONITORING
Line control and monitoring of the CS61584A may
be implemented in either Hardware or Host mode.
Hardware mode is selected when the MODE pin is
set low and allows the device to be configured and
monitored using control pins. Host mode is select-
ed when the MODE pin is set high and allows the
device to be configured and monitored using an in-
ternal register set.
The following controls and indications are avail-
able in Hardware mode: line length selection, re-
ceive clock edge, jitter attenuator location, loss of
signal, transmit all ones, local loopback, remote
loopback, and power down. Host mode operation
offers several additional control options (refer to
the Host Mode section).
Note: Please refer to the Loop Selection Equations in
the Applications section.
8.1 Line Code Encoder/Decoder
Hardware mode supports only transparent opera-
tion to permit the line code to be encoded and de-
coded by an external T1/E1 framing device.
Recovered data is output on the RNEG and RPOS
pins in NRZ format and transmitted data is input on
the TNEG and TPOS pins.
Host mode supports transparent, AMI, B8ZS, or
HDB3 line encoding and decoding for applications
not using an external T1/E1 framer (i.e. multiplex-
ers). The CODER, AMI-T, and AMI-R bits in the
Control A registers select the coder mode for a giv-
en channel. The selection of the transmit encoder is
independent from the selection of the receive de-
coder. When CODER = 1, the transmit data is input
to the encoder on TDATA and the receive data is
output from the decoder on RDATA in NRZ for-
mat.
8.2 Alarm Indication Signal
During Host mode operation, the alarm indication
signal (AIS) is detected by the receiver and report-
ed using the AIS and Latched-AIS bits in the Status
registers. The receiver detects the AIS condition on
observation of 99.9% ones density in a 5.3 ms peri-
od (< 9 zeros in 8192 bits). If CODER = 1 in the
Control A registers, the TNEG pin becomes the
AIS output pin that is set high on detection of AIS.
The AIS condition is exited when
≥
9 zeros are de-
tected in 8192 bits.
CS61584A
20 DS261F1