Cirrus Logic CS61584A - Manual (Page 33)

CS61584A
DS261PP5 33
DS261PP5
Bypass Register: The Bypass register consists of a
single bit, and provides a serial path between J-TDI
and J-TDO, bypassing the BSR. This allows by-
passing specific devices during certain board-level
tests. This also reduces test access times by reduc-
ing the total number of shifts required from J-TDI
to J-TDO.
10.2 JTAG Instructions and Instruction
Register (IR)
The instruction register (2 bits) allows the instruc-
tion to be shifted into the JTAG circuit. The in-
struction selects the test to be performed or the data
register to be accessed or both. The valid instruc-
tions are shifted in LSB first and are listed in
Table 12:
EXTEST Instruction: The EXTEST instruction al-
lows testing of off-chip circuitry and board-level
interconnect. EXTEST connects the BSR to the J-
TDI and J-TDO pins. The normal path between the
CS61584A logic and I/O pins is broken. The sig-
nals on the output pins are loaded from the BSR
and the signals on the input pins are loaded into the
BSR.
SAMPLE/PRELOAD Instruction: The SAM-
PLE/PRELOAD instructions allows scanning of
the boundary-scan register without interfering with
the operation of the CS61584A. This instruction
connects the BSR to the J-TDI and J-TDO pins.
The normal path between the CS61584A logic and
its I/O pins is maintained. The signals on the I/O
pins are loaded into the BSR. Additionally, this in-
struction can be used to latch values into the digital
output pins.
IDCODE Instruction: The IDCODE instruction
connects the device identification register to the J-
TDO pin. The IDCODE instruction is forced into
the instruction register during the Test-Logic-Reset
controller state.The default instruction is IDCODE
after a device reset.
BYPASS Instruction: The BYPASS instruction
connects the minimum length bypass register be-
tween the J-TDI and J-TDO pins and allows data to
be shifted in the Shift-DR controller state.
10.3 JTAG TAP Controller
Figure 24 shows the state diagram for the TAP state
machine. A description of each state follows. Note
that the figure contains two main branches to ac-
cess either the data or instruction registers. The val-
ue shown next to each state transition in this figure
is the value present at J-TMS at each rising edge of
J-TCK.
10.4 Test-Logic-Reset State
In this state, the test logic is disabled to continue
normal operation of the device. During initializa-
tion, the CS61584A initializes the instruction reg-
ister with the IDCODE instruction.
Regardless of the original state of the controller,
the controller enters the Test-Logic-Reset state
when the J-TMS input is held high for at least five
rising edges of J-TCK. The controller remains in
this state while J-TMS is high. The CS61584A pro-
cessor automatically enters this state at power-up.
IR CODE INSTRUCTION
00 EXTEST
01 SAMPLE/PRELOAD
10 IDCODE
11 BYPASS
Table 12.
MSB LSB
31 28 27 12 11 1 0
0 0 0 0 0 1 1 0 0 1 1 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1
4 bits 16 bits 11 bits
BIT #(s) Function Total Bits
31-28 Version Number 4
27-14 Part Number 14
13-12 Derivative Code 2
11-1 Manufacturer Number 11
0 Constant Logic ‘1’ 1
Table 11. Device Identification Register
CS61584A
DS261F1 33