Cirrus Logic CS8952 - Manual (Page 64)

CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 64
DS206F1
plied through the XTAL_I pin, or using an external
clock source supplied through the TX_CLK pin.
When a 25 MHz crystal is used, it should be placed
within one inch of the XTAL_I and XTAL_O pins
of the CS8952. The crystal traces should be short,
have no vias, and run on the component side.
Table 7 lists examples of manufacturers of suitable
crystals. The designer should evaluate their crystal
selection for suitability in their specific design.
An external CMOS clock source may be connected
to the XTAL_I pin, with the XTAL_O pin left
open. The input capacitance of the XTAL_I pin is
larger than the other inputs (a maximum of 35pF),
since it includes the additional load capacitance of
the crystal oscillator. Care should be taken to as-
sure any external clock source attached to XTAL_I
is capable of driving higher capacitive loads. The
clock signal should be 25 MHz ±0.01% with a duty
cycle between 45% and 55%.
When the XTAL_I pin load is a problem, or only a
TTL level clock source is available, the CS8952
can be clocked through the TX_CLK pin, provid-
ing the TX_CLK mode is set appropriately using
the TCM pin. The clock frequency will be depen-
dent on the operating mode.
7.5 Recommended Magnetics
The CS8952 requires an isolation transformer with
a 1:1 turns ratio for both the transmit and receive
signals. Table 7 lists examples of manufacturers
with transformers meeting these requirements.
However, the designer should evaluate the magnet-
ics for suitability in their specific design.
7.6 Power Supply and Decoupling
The CS8952 supports connection to either a 3.3 V
or 5.0 V MII. When connected to a +5.0 V MII, all
power pins should be provided +5.0 V +/- 5%, and
all signal inputs should be referenced to +5.0V.
When interfaced with a 3.3 V MII, VDD_MII pow-
er pins should be provided +3.3 V +/- 5%, VDD
power pins should be provided +5.0 V +/- 5%, and
all signal inputs should be referenced to +3.3 V.
Each CS8952 power pin should be connected to a
0.1 µF bypass capacitor and then to the power
plane. The bypass capacitors should be located as
close to its corresponding power pin as possible.
Connect ground pins directly to the ground plane.
4.99 k Ω
VSS
RES
VSS
CS8952
Via to
Ground Plane
87
86
85
Figure 8. Biasing Resistor Connection and Layout
Component Manufacturer Part Number
Crystal
Raltron Electronics Corp.
10651 NW 19th St.
Miami, FL 33172
(305) 593-6033
www.raltron.com AS-25.000-15-F-
EXT-SMD-TR-
CIR
Transformer
Halo Electronics, Inc.
P.O. Box 5826
Redwood City, CA 94063
USA
(650) 568-5800
www.haloelectronics.com TG22-3506ND
Bel Fuse, Inc.
198 Van Vorst Street
Jersey City, NJ 07302
USA
(201) 432-0463
www.belfuse.com S5558-5999-46
Pulse Engineering
12220 World Trade Drive
San Diego, CA 92128
USA
(619) 674-8100
www.pulseeng.com PE-68515
Fiber
Interface
Hewlett Packard
Component Sales
Response Center
(408) 654-8675
www.hp.com/HP-COMP HFBR-5103
Table 7. Support Component Manufactures