Block diagram, Microcontroller and hex switches, A/d converter – Cirrus Logic EV2 User Manual
Page 22: D/a converter, Connectors and interfaces, Optional vcxo and clock buffers, Aes3 transceiver, Power supply conditioning, Fpga, Cobranet™ ev-2
Rev. 2.1
22
CobraNet™ EV-2
EV-2 Schematics, Page-by-Page Description
The following sections provide detailed descriptions of the EV-2 schematic drawings contained in
Appendix D.
Block Diagram
This page is a hierarchical block diagram showing an overview of all schematic pages and
interconnects between pages.
Microcontroller and Hex Switches
This page shows an 8051-type microcontroller, its connections, and peripherals. Peripherals
include 32kbytes of SRAM, hex switch interface, clock oscillator and programming switch.
A/D Converter
This circuit is based on the Cirrus Logic CS5381 reference design. See the Cirrus Logic
website,
etailed description of
s development
system, the
nd reference design, t
D/A Converter
This circuit is based on the Cirrus Logic CS4398 reference design. See the Cirrus Logic
website,
for a detailed description
and its development
system
. The CS4398 in the EV-2 design runs in stand-alone mode.
Connectors and Interfaces
This page shows the CM interface connectors, P510 and P511, as well as the RS232
interface. The reset switch circuit, SW508 and associated components are also included on
this page.
Optional VCXO and clock buffers
Although the CM produces a high quality master clock, in some applications, the master
clock my be compromised by long or noisy signal paths (i.e. ribbon cable connection). An
optional VCXO circuit is included as an example of re-clocking the master clock (FS512) to
attenuate jitter. The VCXO is not installed on the current EV-2 board. Clock buffers are used
to recondition the clock from the CM.
AES3 Transceiver
This circuit uses the Cirrus Logic
See the Cirrus Logic website,
, for a detailed description of the
evaluation
board, t
runs in AES3 transceiver mode with input sample rate
conversion. For the AES3 tranceiver to operate properly, a valid AES3 signal must be
provided at the AES3 input.
Power Supply Conditioning
The main power connector is a standard ATX connector. The voltage mains are conditioned,
as well as protected with transient voltage suppressor diodes. Numerous voltage regulators
are used to filter and condition the power supplied to the analog audio section.
FPGA
This page shows the connections to the FPGA, which is a Xilinx XCS10XL-4VQ100 IC. See
the FPGA discussion above for a detailed description of its functionality.