Cirrus Logic EV2 - Manual (Page 29)

CobraNet™ EV-2
29 Rev. 2.1
1
2
34
A B C D
4
3
2
1
D C B A
C
o
braN
et (T
M
) E
valuation B
oard
E
2500 55th Street Sui
te 210
T
itle
:
File:
EV
2_M
ain.Sch
19
19-O
ct-2004
Date:
Sheet
of
Engineer: Bill Lowe
www.
peakaudi
o.
com
www.
ci
rrus.
com
Size:
Num
b
er:
Revision:
A
Cirrus Logic, Inc.
B
o
ulder, C
O
80301
MC
L
K
SSI_CLK FS1_OUT
AD_
DATA1
HPF# EN
_96K
AD_RESET#
A
/D
Converter
EV2
_
AD.
sch
AD[0
..
7
]
HACK#
HREQ#
WR
#
M
R
ESET
W
A
TCHDOG
M
U
TE#
TXD
RXD
ALE RD#
A
[8..15]
INIT_IO#
MC
U
_
P
3
5
PROGRAM
#
A
[0..7]
MC
U
_
C
L
K
MC
U
_
P
1
7
U
P
C
a
nd logic
EV
2_8051.sch
FS1_OUT
AD_
DATA1
DA_RESET# DA_
DATA
MC
L
K
SSI_CLK FS1_OUT EN
_96K
DA_
CCLK
DA_
CS#
DA_
CDOUT
D
/A
Converter
EV2
_
DA.
sch
DA_RESET# DA_
DATA
MC
L
K
HACK#
HREQ#
HCS# HRW A
[0..2]
AD[0
..
7
]
M
R
ESET
M
R
ESET#
RSVD[1.
.4
]
M
U
TE#
TXD
RXD
HRESET# SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3
SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3
W
A
TCHDOG
FS512_IN AUX_
POW
ER[0
..
3
]
SCI_CLK
HEN#
ADDR3
FS512_O
U
T
SSI_CLK_IN
FS1_IN
C
o
m
m
on c
o
m
pone
nts
EV
2_c
om
.sc
h
HCS#
HREQ#
HW
R#
HACK# A
[0..2]
AD[0
..
7
]
HRESET# HCS#
M
R
ESET
M
R
ESET#
M
U
TE#
AD[0
..
7
]
HREQ#
HACK# WR
#
RSVD[1.
.4
]
M
R
ESET
M
U
TE#
HPF#
HPF# TXD
DA_
DATA
FS1_OUT HRESET# SSI_CLK SSI_CLK
SSI_CLK
SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3
SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3
W
A
TCHDOG
W
A
TCHDOG
DA_RESET# FS1_OUT
FS512_IN
AUX_
POW
ER[0
..
3
]
SCI_CLK
AD_
DATA1
SSI_DOUT[0.
.3
]
SSI_DIN[0.
.3
]
FS512_O
U
T
FS512_IN SSI_CLK_IN FS1_IN
SSI_CLK FS1_OUT
AES_BCLK
AES_FS1
FS512_CLK
MC
L
K
A
uxiliary
V
X
C
O
EV2_VCXO.
sch
FS512_IN
FS512_O
U
T
FS512_CLK
HEN#
HEN#
RESET# AES_
DOUT
AES_BCLK AES_W
C
LK
AES_DIN
EN
_96K
#
EN
_96K
FS512_O
U
T
AES I/O EV2_AES.
Sch
M
R
ESET#
EN
_96K
#
AES_DIN
AES_DIN
AES_DOUT
AES_
DOUT
AUX_
POW
ER[0
..
3
]
SCI_CLK Power EV
2_pw
r.sch
AES_FS1 AES_BCLK
AES_FS1 AES_BCLK
EN
_96K
AD[0
..
7
]
WR
#
PROGRAM
#
INIT_IO#
HPF#
AUX_
POW
ER[0
..
3
]
ALE SCI_CLK A
[8..15]
RSVD[1.
.4
]
SSI_DOUT[0.
.3
]
SSI_DIN[0.
.3
]
AD_
DATA1
DA_
DATA
AES_DIN
AES_
DOUT
M
U
TE#
RD#
HCS# HEN#
DA_RESET#
HRESET#
MC
U
_
P
3
5
FS512_CLK FS1_OUT MC
U
_
C
L
K
AES_BCLK
HW
R#
A
[0..7]
ADDR3
AD_RESET#
DA_
CDOUT
DA_
CCLK
DA_
CS#
MC
U
_
P
1
7
EN
_96K
EN
_96K
#
CNEV_FPGA EV2_FPGA.
Sch
AD[0
..
7
]
RXD
TXD
WR
#
ALE
ALE A
[8..15]
RD#
RD#
PROGRAM
#
INIT_IO#
INIT_
IO#
PROGRAM
#
A
[8..15]
M
U
TE#
MC
U
_
P
3
5
MC
U
_
P
3
5
RSVD[1.
.4
]
FS512_CLK FS1_OUT MC
U
_
C
L
K
RXD
AES_BCLK
HW
R#
A
[0..7]
A
[0..7]
MC
L
K
ADDR3
ADDR3
EN
_96K
AD_RESET#
AD_RESET#
EN
_96K
MC
U
_
C
L
K
MC
L
K
FS512_O
U
T
DA_
CCLK
DA_
CDOUT
DA_
CS#
DA_
CCLK
DA_
CDOUT
DA_
CS#
MC
U
_
P
1
7
MC
U
_
P
1
7
EN
_96K
EN
_96K
#
FS512_O
U
T
SSI_CLK_IN
SSI_CLK_IN
FS1_IN
FS1_IN
Appendix D: EV-2 Schematic Drawings