Cirrus Logic EV2 - Manual (Page 37)

CobraNet™ EV-2
37 Rev. 2.1
1
2
34
A B C D
4
3
2
1
D C B A
C
o
braN
et (T
M
) E
valuation B
oard - F
P
G
A
E
2500 55th Street Sui
te 210
T
itle
:
File:
EV2_FPGA.
Sch
99
19-O
ct-2004
Date:
Sheet
of
Engineer: Bill Lowe
www.
peakaudi
o.
com
www.
ci
rrus.
com
Size:
Num
b
er:
Revision:
A
Cirrus Logic, Inc.
B
o
ulder, C
O
80301
AD[0.
.7
]
AD[0.
.7
] GND
B
904
.1S
VCC_+3
GND
B
903
.1S
VCC_+3
GND
B
902
.1S
VCC_+3
B
901
.1S
VCC_+3
B
908
.1S
VCC_+3
B
907
.1S
VCC_+3
B
906
.1S
VCC_+3
GND
B
905
.1S
VCC_+3
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
WR
#
WR
#
WR
#
PROGRAM
#
PROGRAM
#
INIT_IO#
INIT_IO#
A
[0..7]
A
[0..7]
A0
A1
A2 A3 A4 A5 A6 A7
LED0
LED1
LED2
AUX_POWER0
AUX_POWER1
AUX_POWER2
AUX_POWER3
AUX_POW
ER[0.
.3
]
AUX_POW
ER[0.
.3
]
ALE
ALE
SCI_CLK
SCI_CLK
A8
A9
A10
A11
A1
2
A1
3
A1
4
A15
ADDR3 RSVD1 RSVD2 RSVD3
RSVD4
RSVD[1.
.4
]
RSVD[1.
.4
]
I/O,
TM
S
6
I/O
3
I/O,
TDI
4
I/O,
TCK
5
I/O
7
I/O
15
I/O
9
I/O
10
GND
11
VCC3
12
I/O
13
I/O
14
I/O
19
M1
22
I/O
16
I/O
20
I/O,
GCK2
21
GND
23
M0
24
VCC3
25
PWRDWN
26
I/O
31
I/O (HDC)
28
I/O
29
I/O (LDC)
30
I/O
32
I/O
33
I/O
39
I/O
34
I/O
41
I/O (INIT)
36
GND
49
GND
38
I/O
40
I/O
42
I/O
43
I/O
44
I/O
46
I/O
47
I/O, GCK4
48
DONE
50
VCC3
51
PROGRAM
52
(D7) I/O
53
I/O
56
(D5) I/O
57
I/O
58
I/O
59
I/O
60
(D4) I/O
61
I/O
62
VCC3
63
(D3) I/O
65
I/O
66
I/O
67
(D2) I/O
68
I/O
90
(DOUT) GCK6,
I/O
73
I/O
69
I/O
78
GCK5,
I/O
54
GND
77
GCK7, I/O
79
(CS1) I/O
80
I/O
82
I/O
83
I/O
84
I/O
85
I/O
86
I/O
87
GND
88
VCC3
89
VCC3
37
I/O
92
I/O
93
I/O
94
I/O
95
I/O
96
I/O
97
I/O
98
GCK8, I/O
99
I/O
18
GND
1
I/O
8
I/O
17
I/O, GCK3
27
I/O
35
I/O
45
(D6) I/O
55
GND
64
I/O
71
I/O
81
I/O
91
VCC3
100
(D1) I/O
70
(D0,
DIN) I/O
72
CCLK
74
VCC3
75
TDO, O
76
I/O,
GCK1
2
U
901
X
C
S10X
L-4V
Q
100
SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3
SSI_DIN[0.
.3
]
SSI_DIN[0.
.3
]
SSI_DOUT[0.
.3
]
SSI_DOUT[0.
.3
]
SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3
AD_DATA1
AD_DATA1
DA_
DATA
DA_
DATA
AES_DIN
AES_DOUT
AES_DIN
AES_DOUT
M
U
TE#
M
U
TE#
C
R
904
LEDPCRED C
R
903
LEDPCGRN C
R
905
LEDPCYLW
+5V
LED0 LED1 LED2
RD#
RD#
HCS#
HCS#
HEN#
HEN#
HRESET#
NC
DA_RESET#
DA_RESET#
HRESET#
MC
U_
P
3
5
MC
U_
P
3
5
FS512_CLK
FS1_OUT
FS1_OUT
FS512_CLK
MC
U_
C
L
K
MC
U_
C
L
K
NC
NC
HWR#
NC
NC
AES_BCLK
AES_BCLK
HWR#
A
[8..15]
A
[8..15]
GND
GND
GND
GND
ADDR3
AD_RESET#
HPF#
HPF#
AD_RESET#
EN_96K
EN_96K
NC
DA_CCLK
DA_CDOUT
DA_CS#
DA_CCLK
DA_CDOUT
DA_CS#
MCU_P17
MCU_P17
R
903
464P1S R
904
464P1S R
905
464P1S
3
4
U
508B
74LV
X
14S
EN
_96K
EN
_96K
#
EN
_96K
#
R
902
1K
P1S
GND GND
GND
GND
GND
GND
GND GND
GND
R
901
51.1P1S