MSI 880G-E45 - Manual (Page 62)

3-22
BIOS Setup
Advance DRAM Configuration
Press <Enter> to enter the sub-menu and the following screen appears.
DRAM Timing Mode
This field has the capacity to automatically detect all of the DRAM timing. If you set
this field to [DCT 0], [DCT 1] or [Both], some fields will appear and selectable. DCT
0 controls channel A and DCT1 controls channel B.
CAS Latency (CL)
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjust-
able. This controls the CAS latency, which determines the timing delay (in clock
cycles) before SDRAM starts a read command after receiving it.
tRCD
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjust-
able. When DRAM is refreshed, both rows and columns are addressed separately.
This setup item allows you to determine the timing of the transition from RAS (row
address strobe) to CAS (column address strobe). The less the clock cycles, the
faster the DRAM performance.
tRP
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjust-
able. This setting controls the number of cycles for Row Address Strobe (RAS) to
be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its
charge before DRAM refresh may be incomplete and DRAM may fail to retain data.
This item applies only when synchronous DRAM is installed in the system.
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