MSI Wind Board D510 - Manual (Page 32)

En-22
MS-7618 Mainboard MS-7618 Mainboard
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Important Important
Enabling the functionality of Hyper-Threading Technology for your computer system
requires ALL of the following platform Components:
CPU: An Intel ® Processor with HT Technology;
Chipset: An Intel ® Chipset that supports HT Technology;
BIOS: A BIOS that supports HT Technology and has it enabled;
OS: An operating system that supports HT Technology.
For more information on Hyper-threading Technology, go to:
http://www.intel.com/products/ht/hyperthreading_more.htm
Execute Bit Support Execute Bit Support
Intel’s Execute Disable Bit functionality can prevent certain classes of malicious
“buff er overfl ow” attacks when combined with a supporting operating system. This
functionality allows the processor to classify areas in memory by where application
code can execute and where it cannot. When a malicious worm attempts to insert
code in the buff er, the processor disables code execution, preventing damage or
worm propagation.
Set Limit CPUID MaxVal to 3 Set Limit CPUID MaxVal to 3
The Max CPUID Value Limit is designed limit the listed speed of the processor to
older operating systems.
Memory-Z Memory-Z
Press <Enter> to enter the sub-menu.
DIMM1~2 Memory SPD Information DIMM1~2 Memory SPD Information
Press <Enter> to enter the sub-menu. The sub-menu displays the informations of
installed memory.
Advance DRAM Confi guration Advance DRAM Confi guration
When the DRAM Timing Mode is set to [Manual], this sub-menu will available. Press
<Enter> to enter the sub-menu.
DRAM Timing Mode DRAM Timing Mode
Select whether DRAM timing is controlled by the SPD (Serial Presence Detect) EEP-
ROM on the DRAM module. Setting to [Auto] enables DRAM timings and the fol-
lowing “Advance DRAM Confi guration” sub-menu to be determined by BIOS based
on the confi gurations on the SPD. Selecting [Manual] allows users to confi gure the
DRAM timings and the following related “Advance DRAM Confi guration” sub-menu
manually.
CAS Latency (CL) CAS Latency (CL)
This controls the CAS latency, which determines the timing delay (in clock cycles)
before SDRAM starts a read command after receiving it.
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