Rockwell Automation 1402-LSM Line Synchronization Module Installation Instructions - Manual (Page 27)

Chapter 3
General Operation
3–5
Synchronization Continued
The “Permissive Synchronization” discrete output from the PLC–5 prevents
the LSM from issuing any error signals, but it asserts the “Close Breaker”
discrete input to the PLC–5 if the synchronization criteria are satisfied. This
mode also recognizes a “dead reference bus” condition and asserts the “Close
Breaker” discrete input to the PLC–5 to allow an operator to bring the
synchronizing bus on line when the reference bus has failed.
The “Enable Single Phase Synchronization” discrete output from the PLC-5
allows for single phase synchronization. In this mode, only the voltages
applied to the V3 inputs of the synchronization bus and reference bus are
used for synchronization. Any voltages applied to the V1 and/or V2 inputs
are not used for synchronization purposes (i.e. phase rotation, dead-bus
conditions and over-voltage conditions). Other than not using the V1 and V2
inputs, single phase synchronization does not change the operation of Auto,
Check or Permissive synchronization functions.
•
Voltage Match Error = 100
 (Reference Bus Voltage – Synchronizing
Bus Voltage) /(Reference Bus Voltage)
•
Frequency Match Error = (Reference Bus Frequency) – ( Synchronizing
Bus Frequency)
•
Phase Match Error = (Reference Bus Voltage Zero–cross Degrees) –
(Synchronizing Bus Voltage Zero–cross Degrees) [This calculation is
performed on either both rising zero–crosses or both falling zero–crosses
and the result is adjusted to provide a value between –180 degrees and
+180 degrees.]
In the “Delayed Acceptance Window” method of synchronization, the “Close
Breaker” discrete input to the PLC–5 is asserted after the “Voltage Match
Error”, the “Frequency Match Error”, and the “Phase Match Error” have all
remained continuously within their respective acceptance windows for the
configured delay time, called: “Acceptance Window Delay”.
In the event the reference bus and synchronizing bus systems are opposite in
phase rotation, the synchronization fails. This is indicated by the
“Synchronization Failure” discrete input to the PLC–5. Additional
information pertaining to the cause of the failure may be obtained by reading
the appropriate block transfer data from the “Synchronizing Bus Error
Parameters” table. (See Appendix B, “Block Transfer and Discrete I/O
Definition”, for additional information.)
Important: While still indicated in single phase synchronization mode,
phase rotation mismatch will not set the “synchronization failure”
discrete input to the PLC-5.
Operational Characteristics
Continued