Cypress CY14B101P - Manual (Page 12)

PRELIMINARY CY14B101P
Document #: 001-44109 Rev. *B Page 12 of 32
WRITE RTC (WRTC) Instruction
WRITE RTC (WRTC) instruction allows the user to modify the
contents of RTC registers. The WRTC instruction requires the
WEN bit to be set to '1' before it can be issued. If WEN bit is '0',
a WREN instruction needs to be issued before using WRTC.
Writing RTC registers requires the following sequence: After the
CS line is pulled LOW to select a device, WRTC opcode is trans-
mitted through the SI line followed by eight address bits identi-
fying the register which is to be written to and one or more bytes
of data. WRTC allows burst mode write operation. When writing
more than one registers in burst mode, the address rolls over to
0x00 after the last RTC address (0x0F) is reached.
Note that writing to RTC timekeeping and control registers
require the W bit to be set to '1'. The values in these RTC
registers take effect only after the W bit is cleared to '0'. Write
Enable bit (WEN) is automatically cleared to ‘0’ after completion
of the WRTC instruction.
nvSRAM Special Instructions
CY14B101P provides four special instructions that allow access
to the nvSRAM specific functions: STORE, RECALL, ASDISB,
and ASENB.
Table 7 lists these instructions.
Software Store (STORE)
When a STORE instruction is executed, CY14B101P performs a
Software Store operation. The STORE operation is issued
irrespective of whether a write has taken place since last STORE
or RECALL operation.
To issue this instruction, the device must be write enabled (WEN
bit = ‘1’).The instruction is performed by transmitting the STORE
opcode on the SI pin following the falling edge of CS. The WEN
Figure 14. Read RTC (RDRTC) Instruction Timing
CS
SCK
SO
0 1 2 3 4 5 6 7 0 3 2 1 4 5 6 7 0 1 2 3 4 5 6 7
MSB LSB Data
SI
Op-Code
0 0 0 1 0 0 1 0 0 0 0 1 A3 A1 A2 A0
MSB LSB
D0 D1 D2 D3 D4 D5 D6 D7
Figure 15. Write RTC (WRTC) Instruction Timing
CS
SCK
SO
0 1 2 3 4 5 6 7 0 3 2 1 4 5 6 7 0 1 2 3 4 5 6 7
SI
Op-Code
0 0 0 1 0 0 1 0 0 0 0 0 A3 A1 A2 A0
4-bit Address
MSB LSB MSB LSB Data
HI-Z
D0 D1 D2 D3 D4 D5 D6 D7
Table 7. nvSRAM Special Instructions
Function Name Opcode Operation
STORE 0011 1100 Software Store
RECALL 0110 0000 Software Recall
ASENB 0101 1001 AutoStore Enable
ASDISB 0001 1001 AutoStore Disable
Figure 16. Software STORE Operation
0 0 1 1 1 1 0 0
CS
SCK
SI
SO
Hi-Z
0 1 2 3 4 5 6 7
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