Kontron NSC2U IP Network Server - Manual (Page 36)

NSC2U Server—Server Component Installations and Upgrades
Kontron IP Network Server NSC2U
Product Guide, rev. 1.4 December 2009
36
To boot the system, the system BIOS on the server board uses a dedicated I 2 C bus to
retrieve the DIMM information needed to program the MCH memory registers. Table 7
provides the I 2 C addresses for each DIMM slot.
3.4.2.1 Memory RASUM Features
The MCH supports several memory Reliability, Availability, Serviceability, Usability, and
Manageability (RASUM) features. These features include the Intel® x4 Single Device
Data Correction (Intel® x4 SDDC) for memory error detection and correction, memory
scrubbing, retry on correctable errors, memory built in self test, DIMM sparing, and
memory mirroring. See the Intel® S5000 Series Chipsets Server Board Family
Datasheet for more information describing these features.
3.4.2.2 Supported Memory
The server board supports up to eight DDR2-533 or DDR2-667 Fully Buffered DIMMs
(FBD memory). The following tables show the maximum memory configurations
supported using the specified memory technology.
Figure 20. DIMM Slots and Channels
TS000270
DIMM D2
DIMM D1
DIMM C2
DIMM C1
DIMM B2
DIMM B1
DIMM A2
DIMM A1
Branch 0
MCH
Channel A
Channel B
Channel D
Channel C
Branch 1
Table 7. I 2 C Addresses for Memory Module SMB
Device Address
DIMM A1 0xA0
DIMM A2 0xA2
DIMM B1 0xA0
DIMM B2 0xA2
DIMM C1 0xA0
DIMM C2 0xA2
DIMM D1 0xA0
DIMM D2 0xA2