CANOGA PERKINS 2270 Fiber Optic Modem - Manual (Page 34)

34
Canoga Perkins
3.9 Programmable Buffered Interface - Model P53
The Model P53 Interface Module employs an RS-422 electrical interface with a DB-25 interface
connector (RS-530). It also employs an 8-bit elastic buffer.
A combination of FIFO (First In, First Out), Delay Line and Inverter circuitry allows you to custom-
ize the configuration for a variety of standard and nonstandard synchronous clocking arrange-
ments.
Interface configuration is accomplished via an on-card wire wrap header (J3) and a four-position
DIP switch. This interface offers flexible control configurations as well as clock and data. The
standard configuration for this interface is DCE with DB-25S connector. Two connector adapters
are provided with each interface. The DCE/DTE adapter converts the physical interface to DTE
with DB-25P. The "Legacy" adapter converts the interface from DCE to the pinout of the original
"P2" interface product.
Figure 3-4 illustrates the resources available for configuring via the J3 wire wrap header. A wide
variety of configurations are possible to satisfy many requirements.
This interface is typically used to interface with encryption devices on the BLACK side where the
modems act as the network and supply clocking in a synchronous configuration, or to interface to
the RED (clear) side of data encryption (KG) equipment. In the RED application, the interface acts
as a "tail-circuit adapter" device. This configuration allows the modem to accept two synchronous
clock (typically, DCE devices only accept one): one for transmit (external clock) and one for
receive (FIFO input clock).
Another common application is with systems that communicate over geosynchronous satellites.
In this application, the FIFO is used to make up for clock drift (doppler shift) caused by the
satellite's elliptical orbit around the Earth.
Figure 3-5 illustrates the location of the J3 programming header, the DIP switches used for setting
the delay line parameter, the interface connectors, the KG Resync control output setting jumpers
and all factory default jumper settings.
The FIFO allows the user to recondition either the received or transmitted data (not both). The
Delay Line, in conjunction with a four-position DIP switch, provides an option for fine-tuning the
relationship between clock and data timing. Table 3-K defines the delay times versus switch
settings for Model P53.