CANOGA PERKINS 2270 Fiber Optic Modem - Manual (Page 51)

51
2270 Fiber Optic Modem
4.6 Bit Count Integrity
The 2270's design enables a much better integrity for the clock than the data. The data Bit Error
Rate (BER) can be summarized as, "no more than one bit error in 10
11 bits." The Bit Count Integrity
(BCI) can be summarized as, "no more than one count missed in 1400 hours."
Figure 4-3.
Data Organization
with PWM Optics
4.7 Duty Cycle Tolerance
The 2270 will accept any clock input duty cycle between 30% and 70%. Above data rates of 9
Mbps, any asymmetrical clock input is corrected to approximately 50% duty cycle. Below this
rate, the duty cycle offset of the input is reproduced at the output. Below 6.5 Mbps, duty cycles
from 25% to 75% can be tolerated.
The 2270 may cause the receive clock duty cycle to be inverted relative to the input clock, but the
clock-to-data phasing will still be correct. This is an artifact of the design method used to ensure
the high BCI.
The 2270's design stresses integrity of clock reproduction. This accounts for the exceedingly high
BCI of less than one error in 10
14 clock cycles at 20 Mbps.
4.8 Control Signals
The 2270 interfaces support limited control signal functions. If Data Set Ready (DSR) is present as
an interface output, it is asserted when the modem is powered and is not in any test or loopback
mode. This standard DSR response functions as a Test Mode indication.
Some interfaces support both DSR and Test Mode (TM). A different DSR signal is made available
to them. Its response complies with EIA and other standards by allowing only one condition for
OFF, that is, only if the modem has received and responded to the command to turn on a remote
loopback.