Cypress CY14B101NA - Manual (Page 11)

PRELIMINARY CY14B101LA, CY14B101NA
Document #: 001-42879 Rev. *B Page 11 of 25
Figure 9. SRAM Write Cycle #2: CE Controlled [3, 18, 19, 21]
Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled [3, 18, 19, 21]
Data Output
Data Input Input Data Valid
High Impedance
Address Valid Address
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SA
t
SCE
t
HA
t
BW
t
PWE
Data Output
Data Input Input Data Valid
High Impedance
Address Valid Address
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SCE
t
SA
t
BW
t
HA
t
AW
t
PWE
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