Pinouts – Cypress CY14B101NA User Manual

Page 3

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PRELIMINARY

CY14B101LA, CY14B101NA

Document #: 001-42879 Rev. *B

Page 3 of 25

Figure 3. Pin Diagram - 48-Pin SSOP and 32-Pin SOIC

Table 1. Pin Definitions

Pin Name

I/O Type

Description

A

0

– A

16

Input

Address Inputs Used to Select one of the 131,072 bytes of the nvSRAM for x8 Configuration.

A

0

– A

15

Address Inputs Used to Select one of the 65,536 words of the nvSRAM for x16 Configuration.

DQ

0

– DQ

7

Input/Output

Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on operation.

DQ

0

– DQ

15

Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on

operation.

WE

Input

Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written

to the specific address location.

CE

Input

Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.

OE

Input

Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read

cycles. I/O pins are tri-stated on deasserting OE HIGH.

BHE

Input

Byte High Enable, Active LOW. Controls DQ

15

- DQ

8

.

BLE

Input

Byte Low Enable, Active LOW. Controls DQ

7

- DQ

0

.

V

SS

Ground

Ground for the Device. Must be connected to the ground of the system.

V

CC

Power

Supply

Power Supply Inputs to the Device. 3.0V +20%, –10%

HSB

[8]

Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.

When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up

resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation HSB is

driven HIGH for short time with standard output high current.

V

CAP

Power

Supply

AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to

nonvolatile elements.

NC

No Connect No Connect. This pin is not connected to the die.

Pinouts

(continued)

NC

A

8

NC
NC

V

SS

DQ6

DQ5
DQ4

V

CC

A

13

DQ3

A

12

DQ2

DQ1

DQ0

OE

A

9

CE

NC

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A

11

A

7

A

14

A

15

A

16

NC

NC

NC

1

2
3
4

5
6
7
8
9

10
11
12
13
14
15
16
17
18
19

20

21
22

23
24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

Top View

(not to scale)

A

10

NC

WE

DQ7

HSB

INT

V

SS

V

CC

V

CAP

NC

45

46

47

48

NC

NC

NC

NC

48-SSOP

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