Cypress CY14B101NA - Manual (Page 12)

PRELIMINARY CY14B101LA, CY14B101NA
Document #: 001-42879 Rev. *B Page 12 of 25
AutoStore/Power Up RECALL
Parameters Description
20 ns 25 ns 45 ns
Unit
Min Max Min Max Min Max
t
HRECALL
[27] Power Up RECALL Duration 20 20 20 ms
t
STORE
[23] STORE Cycle Duration 8 8 8 ms
t
DELAY
[24] Time Allowed to Complete SRAM Cycle 20 25 25 ns
V
SWITCH
Low Voltage Trigger Level 2.65 2.65 2.65 V
t
VCCRISE
VCC Rise Time 150 150 150 µs
V
HDIS
[14] HSB Output Driver Disable Voltage 1.9 1.9 1.9 V
t
LZHSB
HSB To Output Active Time 5 5 5 µs
t
HHHD
HSB High Active Time 500 500 500 ns
Switching Waveforms
Figure 11. AutoStore or Power Up RECALL [27]
V
SWITCH
V
HDIS
V
VCCRISE
t
STORE
t
STORE
t
HHHD
t
HHHD
t
DELAY
t
DELAY
t
LZHSB
t
LZHSB
t
HRECALL
t
HRECALL
HSB OUT
Autostore
POWER-
UP
RECALL
Read & Write
Inhibited
( RWI )
POWER-UP
RECALL
Read & Write BROWN
OUT
Autostore
POWER-UP
RECALL
Read & Write POWER
DOWN
Autostore
Note 23 Note 23
Note 26
Notes
22. t
HRECALL
starts from the time V
CC
rises above V
SWITCH.
23. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
24. On a Hardware STORE, Software STORE / Recall, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t
DELAY
.
25. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V
SWITCH.
26. HSB pin is driven high to VCC only by internal 100kOhm resistor, HSB driver is disabled.
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