ADLINK PCIe-7360 - Manual (Page 50)

40 Operations
Figure 3-12: DO Continuous Mode Architecture
Timing of DO DMA in continuous mode is as shown.
1/N
DO
CL
K
Mux
Int. DO sampled clk
80-step
phase shift
Ext. DO sampled clk
Ext. DO CLK
Mux
Bus Master DMA
100MHz
20kS FIFO Flip Flop
D[31:0]
I
AFI6
SMB CLK in
AFI[7:0]
DO sampled clk
Start Trigger
Mux
NoWait/
WaitTRIG
Software trigger DO-Start
DO Data DO Data
External trigger in
External clock in
clk
enable
80-step
phase shift
O
AFI6
Expo
rt. DO CLK
Mux
SMB CLK out
Exported sampled
clock out
clk valid
Export
clk gate
Software trigger out