ADLINK PCIe-7360 - Manual (Page 58)

48 Operations
Step1: Configuration
X
Define DI port configuration (32/24/16/8-bits data width)
X
Define DI logic level configuration (3.3/2.5/1.8 V)
X
Define DI sample clock configuration (only external)
Z
The phase shift function is available when external clock
is a free-running clock (not a strobe signal) and external
clock rate is from 20 to 100 MHz.
X Define DI-REQ and DI-ACK signal (AFI0 to AFI7)
Z
For example: if configure AFI3 as DI-REQ and AFI4 as
DI-ACK, and then you must connect the handshake sig-
nal (DI-REQ and DI-ACK) of external device to the AFI3
and AFI4.
X Define DI starting mode configuration (NoWait or WaitTRIG)
Z If choose WaitTRIG, you can define start trigger source
to be software trigger or external trigger (DI-Start or
DI-TRIG) from AFI0 to AFI7.
X
Define DI data count