ADLINK PCI-7300A - Manual (Page 28)

20
• Registers
DO_WAIT_NAE (R/W)
0: do not wait output FIFO not almost empty flag
1: delay output data until FIFO is not almost empty
PAT_GEN(R/W)
0: pattern generation disable (FIFO data do not repeat during data output)
1: pattern generation enable (FIFO data repeat themselves during data
output)
DO_WAIT_TRIG (R/W)
0: delay output data until DOTRIG is actived
1: start output data immediately
PB_TERM_OFF (R/W)
0: PORTB terminator ON
1: PORTB terminator OFF
PG_STOP_TRIG (R/W)
0: no effect
1: Stop pattern generation when DOTRIG is deasserted
DO_EN (R/W)
0: Disable digital outputs
1: Enabled digital outputs
DO_FIFO_CLR (R/W)
0: No effect
1: Clear digital output FIFO. If both PORTA and PORTB are configured as
outputs, both FIFO will be cleared. Always get 0 when read.
DI_UNDER (R/W)
0: DO FIFO does not empty during data output
1: DO FIFO is empty during data output, some output data may be outp ut
twice. Write 1 to clear this bit
DO_FIFO_FULL (RO)
0: DO FIFO is not full
1: DI FIFO is full
DO_FIFO_EMPTY (RO)
0: DO FIFO is not empty
1: DO FIFO is empty