ADLINK PCI-7300A - Manual (Page 36)

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• Operation Theory
AUX DI 3..0: Four auxiliary digital inputs
DITRIG: Digital input trigger line
DIACK/DIREQ: Digital input handshaking signals
DOTRIG:
Digital output trigger line
DOACK/DOREQ:Digital output handshaking signals
4.3 Digital I/O Data Flow
When applying digital input functions, the data will be sampled into the input
FIFO periodically as we configured and then transfer to the system memory by
the bus mastering DMA of the PCI Bridge. Figure 4.2 show the data flow of the
16-bit digital input operation.
Figure 4.2 Data flow of digital input
On the other hand, Figure 4.3 shows the data flow of 16-bit digital output
operation. After the bus mastering DMA of the PCI Bridge transfers the output
data to the output FIFO, the cPCI/PCI-7300A will output the data to the
external devices in a pre-assigned period.
Figure 4.3 Data flow of digital output
The width of local data bus on the cPCI/PCI-7300A can be programmable to
be 8-bit, 16-bit or 32-bit. The default data width is 16-bit. Port A is default to be
input port, and Port B is default to be output one. When 8-bit data width is
applied, only the lower byte of the bus will be used. While we program the data
width to be 32-bit, the two ports will operate in the same manner.