Echelon NodeBuilder FX - Manual (Page 17)

NodeBuilder FX User's Guide 3
• Improved performance for arithmetic operations.
• User-programmable interrupts.
• Additional I/O model support.
The following sections describe these new features and functions.
Backwards Compatibility for Device Applications
The 5000 Series chips are compatible with device applications written for 3150 and 3120 Neuron
Chips and Smart Transceivers. You can use the NodeBuilder tool to port your old application to a
5000 Series chip. To do this, you open the device’s NodeBuilder project, update the Neuron Chip
model used by the hardware template to the Neuron 5000 processor or FT 5000 Smart Transceiver, and
then re-build the device application. See Editing Hardware Templates in Chapter 5 for more
information on using the Hardware Template Editor.
You can also use the NodeBuilder tool to upgrade your existing device applications to the new Version
3 code templates when porting them to a 5000 Series chip. The version 3 code templates include
improved code size, speed, and compliance with interoperability guidelines. To upgrade existing
device applications to the version 3 templates, see Using Code Wizard Templates in Chapter 6.
Notes:
The Neuron firmware contains the implementation of the ISO/IEC 14908-1 protocol stack, the
application scheduler, and many frequently used functions. The functions included in the Neuron
firmware vary between firmware versions and chip models; therefore, when you rebuild an existing
application for a FT 5000 Smart Transceiver, the application may have a smaller or larger memory
footprint, subject to the application’s use of library functions.
The Neuron C Version 2.2 language includes the following new keywords: interrupt, __lock,
stretchedtriac, __slow, __fast, and __parity. Some of these keywords use a double underscore
prefix to avoid any naming collisions within existing device applications.
Improved Memory Architecture
The 5000 Series chips have a new memory architecture that speeds up the CPU operation and lowers
development and device costs. The 5000 Series chips have internal on-chip memory that includes 16
KB of ROM to store the Neuron firmware image and 64 KB of RAM (44 KB is available for
application code and data). The 5000 Series chips use external serial memory (EEPROM or flash) to
store your application code, configuration data, and an upgradable Neuron firmware image (the 5000
Series chips have no user-accessible on-chip non-volatile memory). The external serial EEPROM and
flash memory devices communicate with Neuron 5000 Core via a serial peripheral interface bus (SPI)
or Inter-Integrated Circuit (I
2 C) interface. EEPROM devices can use either the SPI or I 2 C interfaces;
flash devices must use the SPI interface.
When a device is reset, the application code and configuration data are copied from the external
non-volatile memory into the internal on-chip RAM, and the device application is then executed. The
5000 Series chips require at least 2KB of off-chip EEPROM to store configuration data, and you can
use a larger capacity EEPROM device or an additional flash device (up to 64 KB) to store your
application code and an upgradable Neuron firmware image.
The 5000 Series chips also include a new interrupt processor (ISR) that handles user-programmable
interrupts, which improves chip performance.
Note: Many types of EEPROM devices are supported; however, Echelon currently supports and
provides drivers for three external flash devices: Atmel AT25F512AN, ST M25P05-AVMN6T, and
SST25VF512A. You can configure the external non-volatile memory used by a device in the
Hardware Template Editor. For more information on using the Hardware Template Editor, see Using
Hardware Templates in Chapter 5.
The following graphic illustrates the memory architecture of the 5000 Series chips. For more
information on the memory architecture of the 5000 Series chips, see the 5000 Series Chip Data Book.