Data interface signals and corresponding clocks – Altera GPIO User Manual
Page 13
Data Interface Signals and Corresponding Clocks
The following table shows the data interface signals and the corresponding clocks.
Table 3: Data Interface Signals and Corresponding Clocks
Signal Name
Configuration
Clock
din
Register Mode: Simple
Register/DDIO
ck
Half-rate: not used
Separate Clocks: Off
Register Mode: DDIO
ck_hr
Half rate: used
Separate Clocks: off
Register Mode: Simple
Register/DDIO
ck_in
Half rate: not used
Separate Clocks: on
Register Mode: DDIO
ck_hr_in
Half rate: used
Separate Clocks: on
dout/oe
Register Mode: Simple
Register/DDIO
ck
Half rate: not used
Separate Clocks: off
Register Mode: DDIO
ck_hr
Half rate: used
Separate Clocks: off
Register Mode: Simple
Register/DDIO
ck_out
Half rate: not used
Separate Clocks: on
Register Mode: DDIO
ck_hr_out
Half rate: used
Separate Clocks: on
ug-altera_gpio
2014.08.18
Data Interface Signals and Corresponding Clocks
13
Altera GPIO IP Core User Guide
Altera Corporation