Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core - Manual (Page 9)

Each output clock has a set of requested settings where you can specify the desired values for output
frequency, phase shift, and duty cycle. The desired settings are the settings that you want to implement in
your design.
The actual values for the frequency, phase shift, and duty cycle are the closest settings (best approximate
of the desired settings) that can be implemented in the PLL circuit.
Reference Clock Switchover
The reference clock switchover feature allows the PLL to switch between two reference input clocks. Use
this feature for clock redundancy, or for a dual clock domain application such as in a system. The system
can turn on a redundant clock if the primary clock stops running.
Using the reference clock switchover feature, you can specify the frequency for the second input clock,
and select the mode and delay for the switchover.
The clock loss detection and reference clock switchover block has the following functions:
• Monitors the reference clock status. If the reference clock fails, the clock automatically switches to a
backup clock input source. The clock updates the status of the
clkbad
and
activeclk
signals to alert
the event.
• Switches the reference clock back and forth between two different frequencies. Use the
extswitch
signal to manually control the switch action. After a switchover occurs, the PLL may lose lock
temporarily and go through the reckoning process.
PLL-to-PLL Cascading
If you cascade PLLs in your design, the source (upstream) PLL must have a low-bandwidth setting, while
the destination (downstream) PLL must have a high-bandwidth setting. During cascading, the output of
source PLL serves as the reference clock (input) of the destination PLL. The bandwidth settings of
cascaded PLLs must be different. If the bandwidth settings of the cascaded PLLs are the same, the
cascaded PLLs may amplify phase noise at certain frequencies.
The
adjpllin
input clock source is used for inter-cascading between fracturable fractional PLLs.
Ports
Table 6: Altera IOPLL Ports
Parameter Type Condition Description
refclk
Input Required The reference clock source that drives the I/O
PLL.
rst
Input Required The asynchronous reset port for the output
clocks. Drive this port high to reset all output
clocks to the value of 0.
UG-01155
2015.05.04
Reference Clock Switchover 9
Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide Altera Corporation
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