Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 161)

The following table specifies the control and status registers that you can access over the Avalon-MM
PHY management interface. A single address space provides access to all registers.
Note: Unless otherwise indicated, the default value of all registers is 0.
Note: Writing to reserved or undefined register addresses may have undefined side effects.
B-2 10GBASE-KR PHY Register Definitions
UG-01172
2015.05.04
Altera Corporation Arria 10 10GBASE-KR Registers
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