Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 28)

Figure 2-3: IP Core Generated Files
Notes:
1. If generated for your IP variation
<Project Directory>
<your_ip>_sim - IP core simulation files
<simulator_vendor >
<simulator setup scripts>
<your_ip>.qip - Quartus II IP integration file
<your_ip>.sip - Lists files for simulation
<your_ip> _example_design - Testbench and example project1
<your_ip>.v, .sv, or .vhd - Top-level IP synthesis file
<tyour_ip>.v
<your_ip>_syn.v or .vhd - Timing & resource estimation netlist1
<your_ip>.cmp - VHDL component declaration file
<your_ip>.bsf - Block symbol schematic file
<your_ip> - IP core synthesis files
<your_ip>.sv, .v, or .vhd - HDL synthesis files
<your_ip>.sdc - Timing constraints file
<your_ip>.ppf - XML I/O pin information file
<your_ip>.spd - Combines individual simulation scripts
<your_ip>_sim.f - Refers to simulation models and scripts
Files Generated for Arria 10 Variations
The Quartus II software version 14.0 Arria 10 Edition and later generates the following IP core output file
structure when targeting Arria 10 devices.
2-14 Files Generated for Arria 10 Variations
UG-01172
2015.05.04
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