Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 179)

Word Addr Bit R/W Name Description
0x4D5
27:24 R
RXEQ CTLE Setting
Most recent
ctle_rc
setting sent to the reconfig
bundle during RX equalization.
29:28 R
RXEQ CTLE Mode
Most recent
ctle_mode
setting sent to the reconfig
bundle during RX equalization.
31:30 R
RXEQ DFE Mode
Most recent
dfe_mode
setting sent tothe reconfig
bundle during RX equalization.
B-20 10GBASE-KR PHY Register Definitions
UG-01172
2015.05.04
Altera Corporation Arria 10 10GBASE-KR Registers
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