Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 29)

Figure 2-4: IP Core Generated Files
<your_ip>.cmp - VHDL component declaration file
<your_ip>.ppf - XML I/O pin information file
<your_ip>.qip - Lists IP synthesis files
<your_ip>.sip - Lists files for simulation
<your_ip>.v or .vhd
Top-level IP synthesis file
<your_ip>.v or .vhd
Top-level simulation file
<simulator_setup_scripts>
<your_ip>.qsys - System or IP integration file
<your_ip>_bb.v - Verilog HDL black box EDA synthesis file
<your_ip>_inst.v or .vhd - Sample instantiation template
<your_ip>_generation.rpt - IP generation report
<your_ip>.debuginfo - Contains post-generation information
<your_ip>.html - Connection and memory map data
<your_ip>.bsf - Block symbol schematic
<your_ip>.spd - Combines individual simulation scripts
<your_ip>.sopcinfo - Software tool-chain integration file
<project directory>
<your_ip>
IP variation files
<your_ip>_example_design
Example location for your IP core testbench and
example project files. The default location is
alt_eth_ultra_0_example_design, but
you are prompted to specify a different path
sim
Simulation files
synth
IP synthesis files
<EDA tool name>
Simulator scripts
<ip subcores>n
Subcore libraries
sim
Subcore
Simulation files
synth
Subcore
synthesis files
<HDL files>
<HDL files>
<your_ip>n
IP variation files
Table 2-4: IP Core Generated Files (Arria 10 Variations)
File Name Description
<my_ip>.qsys The Qsys system or top-level IP variation file. <my_ip> is the name
that you give your IP variation.
UG-01172
2015.05.04
Files Generated for Arria 10 Variations 2-15
Getting Started Altera Corporation
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