Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 757)

VHDL AXI3 and AXI4 Test Programs
VHDL AXI3 Master BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 737
September 2013
procedure set_write_address_ready_delay(id : integer; path_id : in
axi_path_t; signal tr_if : inout axi_vhd_if_struct_t);
procedure set_read_address_ready_delay(id : integer; signal tr_if :
inout axi_vhd_if_struct_t);
procedure set_read_address_ready_delay(id : integer; path_id : in
axi_path_t; signal tr_if : inout axi_vhd_if_struct_t);
procedure set_write_data_ready_delay(id : integer; signal tr_if : inout
axi_vhd_if_struct_t);
procedure set_write_data_ready_delay(id : integer; path_id : in
axi_path_t; signal tr_if : inout axi_vhd_if_struct_t);
procedure set_wr_resp_valid_delay(id : integer; signal tr_if : inout
axi_vhd_if_struct_t);
procedure set_wr_resp_valid_delay(id : integer; path_id : in axi_path_t;
signal tr_if : inout axi_vhd_if_struct_t);
procedure set_read_data_valid_delay(id : integer; signal tr_if : inout
axi_vhd_if_struct_t);
procedure set_read_data_valid_delay(id : integer; path_id : in
axi_path_t; signal tr_if : inout axi_vhd_if_struct_t);
-- Procedure : do_byte_read
-- Procedure to provide read data byte from memory at particular input
-- address
procedure do_byte_read(addr : in std_logic_vector(AXI_MAX_BIT_SIZE-1
downto 0); data : out std_logic_vector(7 downto 0)) is
begin
data := mem(to_integer(addr));
end do_byte_read;
-- Procedure : do_byte_write
-- Procedure to write data byte to memory at particular input address
procedure do_byte_write(addr : in std_logic_vector(AXI_MAX_BIT_SIZE-1
downto 0); data : in std_logic_vector(7 downto 0)) is
begin
mem(to_integer(addr)) := data;
end do_byte_write;
-- Procedure : set_write_address_ready_delay
-- This is used to set write address phase ready delay to extend phase
procedure set_write_address_ready_delay(id : integer; signal tr_if :
inout axi_vhd_if_struct_t) is
begin
set_address_ready_delay(1, id, index, tr_if);
end set_write_address_ready_delay;
procedure set_write_address_ready_delay(id : integer; path_id : in
axi_path_t; signal tr_if : inout axi_vhd_if_struct_t) is
begin
set_address_ready_delay(1, id, index, path_id, tr_if);
end set_write_address_ready_delay;
-- Procedure : set_read_address_ready_delay
-- This is used to set read address phase ready delay to extend phase
procedure set_read_address_ready_delay(id : integer; signal tr_if :
inout axi_vhd_if_struct_t) is
begin
set_address_ready_delay(1, id, index, tr_if);
end set_read_address_ready_delay;
procedure set_read_address_ready_delay(id : integer; path_id : in
axi_path_t; signal tr_if : inout axi_vhd_if_struct_t) is