Estimating power while creating the fpga design – Altera PowerPlay Early Power Estimator User Manual
Page 11
Altera Corporation
2–3
May 2008
PowerPlay Early Power Estimator For Arria GX FPGAs
Setting Up PowerPlay Early Power Estimator
Estimating Power While Creating the FPGA Design
When the FPGA design is partially complete, you can use the PowerPlay
Early Power Estimator file (<revision name>_early_pwr.csv) generated by
the Quartus II software to supply information to the PowerPlay Early
Power Estimator. After importing the power estimation file information
into the PowerPlay Early Power Estimator, you can edit the PowerPlay
Early Power Estimator spreadsheet to reflect the device resource
estimates for the final design.
f
For more information on generating the power estimation file in the
Quartus II software, refer to the PowerPlay Power Analysis chapter in the
Quartus II Handbook.
Table 2–2
shows the advantages and disadvantages of using the
PowerPlay Early Power Estimator spreadsheet for an FPGA design that
is partially complete.
Use the following steps to estimate power usage with the PowerPlay
Early Power Estimator spreadsheet if your FPGA design is partially
complete.
1.
Compile the partial FPGA design in the Quartus II software.
2.
Generate the PowerPlay Early Power Estimator file (<revision
name>_early_pwr.csv) in the Quartus II software by clicking
Generate PowerPlay Early Power Estimator File
on the Project
menu.
3.
Download the PowerPlay Early Power Estimator spreadsheet from
the Altera website.
4.
Import the PowerPlay Early Power Estimator file into the
PowerPlay Early Power Estimator spreadsheet to automatically
populate the PowerPlay Early Power Estimator spreadsheet entries.
Table 2–2. Power Estimation When FPGA Design Is Partially Complete
Advantages
Disadvantages
●
Power estimation can be done early
in the FPGA design cycle
●
Provides the flexibility to
automatically fill in the PowerPlay
Early Power Estimator spreadsheet
based on Quartus II software
compilation results
Accuracy is dependent on user input
and estimate of the final design device
resources