Altera PowerPlay Early Power Estimator - Manual (Page 41)

Altera Corporation 3–27
May 2008 PowerPlay Early Power Estimator For Arria GX FPGAs
Using the PowerPlay Early Power Estimator
Figure 3–18 shows the Global & Other Fast Signals report from the
Quartus II software Compilation Report for an example design. The
report shows the fanout for each signal that uses a global clock. The
Timing Analysis
section of the Compilation Report lists the clock signal
frequencies. Enter the appropriate information from the Compilation
Report into the PowerPlay Early Power Estimator.
Figure 3–19 shows the
PowerPlay Early Power Estimator spreadsheet and the estimated power
consumed by clocks for this design.
Figure 3–18. Global and Other Fast Signals Resource Section in Compilation Report
Global Enable % Enter the average % of time that the entire clock tree is enabled. Each global clock
buffer has an enable signal that can be used to dynamically shut down the entire clock
tree.
Local Enable % Enter the average % of time that clock enable is high for destination flip flops. Local
clock enables for flip flops in ALMs are promoted to LAB-wide signals. When a given flip
flop is disabled, the LAB-wide clock is also disabled, cutting clock power in addition to
power for down-stream logic. This sheet models only the impact on clock tree power.
Total Power (W) This is the total power dissipation due to clock distribution (in W). This value is
calculated automatically.
User Comments Enter any comments. This is an optional entry.
Table 3–9. Clock Section Information (Part 2 of 2)
Column Heading Description