Altera PowerPlay Early Power Estimator - Manual (Page 24)

3–10 Altera Corporation
PowerPlay Early Power Estimator For Arria GX FPGAs May 2008
PowerPlay Early Power Estimator Inputs
Data Width Enter the width of the data for the RAM block. This value is limited based on the
RAM type. The width of the RAM block can be found in the Port A Width or the Port
B Width column of the Quartus II Compilation Report. In the Compilation Report,
select Fitter, and click Resource Section. Click RAM Summary.
For RAM blocks that have different widths for port A and port B, use the larger of
the two widths.
This number must be an integer. The valid range for each RAM type is:
● 1-18 for M512
● 1-36 (1-18 for True Dual-Port) for M4K
● 1-144 (1-72 for True Dual-Port) for MRAM
RAM Mode Select from the following modes:
● Single-Port
● Simple Dual-Port
● True Dual-Port
● ROM
The mode is based on how the Quartus II Compiler implements the RAM. If you are
unsure how your memory module is implemented, Altera recommends compiling a
test case in the required configuration in the Quartus II software. The RAM mode
can be found in the Mode column of the Quartus II Compilation Report.
In the Compilation Report, select Fitter, and click Resource Section. Click RAM
Summary.
A single-port RAM has one port with a R/W control signal. A simple dual-port RAM
has one read port and one write port. A true dual-port RAM has two ports, each with
a R/W control signal. ROMs are read-only single-port RAMs.
Port A – Clock Freq Enter the clock frequency for port A of the RAM block(s) in MHz. This value is
limited by the maximum frequency specification for the RAM type and device
family.
Port A – Enable % Enter the average percentage of time the input clock enable for port A is active,
regardless of activity on RAM data and address inputs. The enable percentage
ranges from 0 to 100%. The default is set to 25%.
RAM power is primarily consumed when a clock event occurs. Using a clock enable
signal to disable a port when no read or write operation is occurring can result in
significant power savings.
Table 3–3. RAM Section Information (Part 2 of 4)
Column Heading Description