Altera Stratix IV GX FPGA - Manual (Page 32)

6–8 Chapter 6: Board Test System
Using the Board Test System
Stratix IV GX FPGA Development Kit User Guide March 2014 Altera Corporation
The SRAM&Flash Tab
The SRAM&Flash tab allows you to read and write SRAM and flash memory on your
board.
Figure 6–4 shows the SRAM&Flash tab.
The following sections describe the controls on the SRAM&Flash tab.
SRAM
The SRAM control allows you to read and write the SRAM on your board. Type a
starting address in the text box and click Read. Values starting at the specified address
appear in the table. The SRAM addresses display in the format the Nios II processor
within the FPGA uses, that is, each SRAM address is offset by 0x00400000. Thus, the
first location in SRAM appears as 0x00400000 in the GUI.
1
If you enter an address outside of the 0x00400000 to 0x005FFFFF SRAM address
space, a warning message identifies the valid SRAM address range.
Figure 6–4. The SRAM&Flash Tab