Altera Cyclone II FPGA Starter Development Board - Manual (Page 41)

Altera Corporation Reference Manual 2–23
October 2006 Cyclone II FPGA Starter Development Board
Development Board Components
Figure 2–18. Seven-Segment Display Schematic Diagram
Seven-Segment Display Pin List
Table 2–13 lists the FPGA pins assigned to the display segments.
Table 2–13. Seven-Segment Display FPGA Pin Connections (Part 1 of 2)
Signal Name FPGA Pin Description
HEX0[0] PIN_J2 Seven-Segment segment 0[0]
HEX0[1] PIN_J1 Seven-Segment segment 0[1]
HEX0[2] PIN_H2 Seven-Segment segment 0[2]
HEX0[3] PIN_H1 Seven-Segment segment 0[3]
HEX0[4] PIN_F2 Seven-Segment segment 0[4]
HEX0[5] PIN_F1 Seven-Segment segment 0[5]
HEX0[6] PIN_E2 Seven-Segment segment 0[6]
HEX1[0] PIN_E1 Seven-Segment segment 1[0]
HEX1[1] PIN_H6 Seven-Segment segment 1[1]