Altera Cyclone V GX FPGA Development Board - Manual (Page 10)

2–2 Chapter 2: Board Components
Board Overview
Cyclone V GX FPGA Development Board May 2013 Altera Corporation
Reference Manual
Board Overview
This section provides an overview of the Cyclone V GX FPGA development board,
including an annotated board image and component descriptions.
Figure 2–1 shows
an overview of the board features.
Table 2–1 describes the components and lists their corresponding board references.
Figure 2–1. Overview of the Cyclone V GX FPGA Development Board Features
Clock Input SMA
Connector
(J16, J17)
Max V Reset
Push Button (S1)
General User
Push Buttons
(S3-S5)
Flash x16
Memory (U18)
PCI Express Edge
Connector (J19)
DDR3B x32
+ ECC Memory
(U6, U15, U19)
DDR3A x32
+ ECC Memory
(U21, U22, U23)
DC Input
Jack (J9)
Character
LCD (J18)
CPU Reset
Push Button (S2)
Power
Switch
(SW1)
User LEDs
(D4-D7)
MAX V CPLD
EPM2210 System
Controller (U12)
Clock Output
SMA Connector
(J4)
HSMC Port
(J1)
Configuration Done,
Load, and Error
LEDs (D15-D17)
Program Config,
Program Select
Push Buttons
(S6, S7)
Program Select
LEDs (D12-D14)
Transceiver SMA
Connectors
RX (J2, J6)
TX (J3, J7)
USB Type-B
Connector (J12)
SDI Video
Port (J5, J10)
Debug Header
(J14)
Gigabit Ethernet
Port (J11)
JTAG Chain
Header
(J13)
Fan Power
Header (J8)
PCI Express
Mode
DIP Switch (SW4)
JTAG Chain
Control
DIP Switch (SW5)
Board Settings
DIP switch (SW3)
Cyclone V GX
FPGA (U11)
Table 2–1. Board Components (Part 1 of 3)
Board Reference Type Description
Featured Devices
U11 FPGA Cyclone V GX, 5CGXFC7D6F31C7NES, 896-pin FBGA.
U12 CPLD MAX V CPLD, 5M2210ZF256C4N, 256-pin FBGA.
Configuration, Status, and Setup Elements
J13 JTAG chain header
Provides access to the JTAG chain and disables the embedded
USB-Blaster II when using an external USB-Blaster cable.
SW5 JTAG chain control DIP switch Remove or include devices in the active JTAG chain.
J12 USB type-B connector
USB interface for FPGA programming and debugging through the
embedded USB-Blaster II JTAG via a type-B USB cable.