Fpga configuration, Fpga configuration –10 – Altera Cyclone V GX FPGA Development Board User Manual
Page 18
2–10
Chapter 2: Board Components
FPGA Configuration
Cyclone V GX FPGA Development Board
May 2013
Altera Corporation
Reference Manual
FPGA Configuration
This section describes the FPGA, flash memory, and MAX V CPLD 5M2210 System
Controller device programming methods supported by the Cyclone V GX FPGA
development board.
The Cyclone V GX development board supports the following three configuration
methods:
■
Embedded USB-Blaster is the default method for configuring the FPGA using the
Quartus II Programmer in JTAG mode with the supplied USB cable.
■
Flash memory download for configuring the FPGA using stored images from the
flash memory on either power-up or pressing the program configuration
push button (S6).
■
External USB-Blaster for configuring the FPGA using an external USB-Blaster that
connects to the JTAG chain header (J13).
K5
SDI_SCL
2.5-V
SDI clock
L16
SDI_SDA
2.5-V
SDI data
N16
SDI_TX_EN
2.5-V
SDI transmit enable
R12
SECURITY_MODE
2.5-V
DIP switch for the embedded USB-Blaster II to send FACTORY
command at power up
K16
SENSE_CS0N
2.5-V
Power monitor chip select
H1
SENSE_SCK
2.5-V
Power monitor SPI clock
G12
SENSE_SDI
2.5-V
Power monitor SPI data in
C14
SENSE_SDO
2.5-V
Power monitor SPI data out
J1
SI571_EN
2.5-V
Si571 programmable VCXO enable
R8
USB_CFG0
2.5-V
Embedded USB-Blaster II interface. Reserved for future use
T7
USB_CFG1
2.5-V
Embedded USB-Blaster II interface. Reserved for future use
R4
USB_CFG2
2.5-V
Embedded USB-Blaster II interface. Reserved for future use
R9
USB_CFG3
2.5-V
Embedded USB-Blaster II interface. Reserved for future use
T11
USB_CFG4
2.5-V
Embedded USB-Blaster II interface. Reserved for future use
T15
USB_CFG5
2.5-V
Embedded USB-Blaster II interface. Reserved for future use
T13
USB_CFG6
2.5-V
Embedded USB-Blaster II interface. Reserved for future use
T9
USB_CFG7
2.5-V
Embedded USB-Blaster II interface. Reserved for future use
T10
USB_CFG8
2.5-V
Embedded USB-Blaster II interface. Reserved for future use
T4
USB_CFG9
2.5-V
Embedded USB-Blaster II interface. Reserved for future use
T8
USB_CFG10
2.5-V
Embedded USB-Blaster II interface. Reserved for future use
T12
USB_CFG11
2.5-V
Embedded USB-Blaster II interface. Reserved for future use
H5
USB_CLK
2.5-V
Embedded USB-Blaster II interface clock
Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 5 of 5)
Board
Reference (U12)
Schematic Signal Name
I/O Standard
Description