Altera Cyclone V GX FPGA Development Board - Manual (Page 45)

Chapter 2: Board Components 2–37
Memory
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
K2 DDR3A_A3 AH12 1.5-V SSTL Class I Address bus
L8 DDR3A_A4 AG13 1.5-V SSTL Class I Address bus
L2 DDR3A_A5 AG14 1.5-V SSTL Class I Address bus
M8 DDR3A_A6 AK10 1.5-V SSTL Class I Address bus
M2 DDR3A_A7 AK11 1.5-V SSTL Class I Address bus
N8 DDR3A_A8 AF11 1.5-V SSTL Class I Address bus
M3 DDR3A_A9 AG11 1.5-V SSTL Class I Address bus
H7 DDR3A_A10 AJ8 1.5-V SSTL Class I Address bus
M7 DDR3A_A11 AK8 1.5-V SSTL Class I Address bus
K7 DDR3A_A12 AJ7 1.5-V SSTL Class I Address bus
N3 DDR3A_A13 AK7 1.5-V SSTL Class I Address bus
J2 DDR3A_BA0 AH9 1.5-V SSTL Class I Bank address bus
K8 DDR3A_BA1 AH10 1.5-V SSTL Class I Bank address bus
J3 DDR3A_BA2 AJ10 1.5-V SSTL Class I Bank address bus
G3 DDR3A_CASN AF9 1.5-V SSTL Class I Row address select
G9 DDR3A_CKE AK18 1.5-V SSTL Class I Column address select
G7 DDR3A_CLK_N Y13 1.5-V SSTL Class I Differential output clock
F7 DDR3A_CLK_P AA14 1.5-V SSTL Class I Differential output clock
H2 DDR3A_CSN Y12 1.5-V SSTL Class I Chip select
B7 DDR3A_DM4 AG23 1.5-V SSTL Class I Write mask byte lane
E3 DDR3A_DQ32 AG21 1.5-V SSTL Class I Data bus byte lane 4
C8 DDR3A_DQ33 AF20 1.5-V SSTL Class I Data bus byte lane 4
E7 DDR3A_DQ34 AK27 1.5-V SSTL Class I Data bus byte lane 4
B3 DDR3A_DQ35 AH26 1.5-V SSTL Class I Data bus byte lane 4
D2 DDR3A_DQ36 AG22 1.5-V SSTL Class I Data bus byte lane 4
C7 DDR3A_DQ37 AF21 1.5-V SSTL Class I Data bus byte lane 4
E8 DDR3A_DQ38 AE22 1.5-V SSTL Class I Data bus byte lane 4
C2 DDR3A_DQ39 AH22 1.5-V SSTL Class I Data bus byte lane 4
D3 DDR3A_DQS_N4 AD20
Differential 1.5-V SSTL
Class I
Data strobe P byte lane 4
C3 DDR3A_DQS_P4 AC21
Differential 1.5-V SSTL
Class I
Data strobe N byte lane 4
G1 DDR3A_ODT AH14 1.5-V SSTL Class I On-die termination enable
F3 DDR3A_RASN AG9 1.5-V SSTL Class I Row address select
N2 DDR3A_RESETN AK21 1.5-V SSTL Class I Reset
H3 DDR3A_WEN AK5 1.5-V SSTL Class I Write enable
H8 DDR3A_ZQ05 — 1.5-V SSTL Class I ZQ impedance calibration
Table 2–29. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Board Reference
Schematic
Signal Name
Cyclone V GX
Pin Number
I/O Standard Description