Altera Data Conversion HSMC - Manual (Page 26)

A–2 Appendix A: Pin-Out Information for the Cyclone III (3C120)
Development Board
Data Conversion HSMC Reference Manual © November 2008 Altera Corporation
66 LVDS RX bit 3p or CMOS I/O data bit 17 ADB_D5 HSMA_RX_D_P3 LVDS or
2.5 V
W2
67 LVDS TX bit 3n or CMOS I/O data bit 18 ADA_D4 HSMA_TX_D_N3 LVDS or
2.5 V
R4
68 LVDS RX bit 3n or CMOS I/O data bit 19 ADB_D4 HSMA_RX_D_N3 LVDS or
2.5 V
W1
71 LVDS TX bit 4p or CMOS I/O data bit 20 ADA_D3 HSMA_TX_D_P4 LVDS or
2.5 V
M8
72 LVDS RX bit 4p or CMOS I/O data bit 21 ADB_D3 HSMA_RX_D_P4 LVDS or
2.5 V
V2
73 LVDS TX or 4n CMOS I/O data bit 22 ADA_D2 HSMA_TX_D_N4 LVDS or
2.5 V
M7
74 LVDS RX 4n or CMOS I/O data bit 23 ADB_D2 HSMA_RX_D_N4 LVDS or
2.5 V
V1
77 LVDS TX 5p or CMOS I/O data bit 24 ADA_D1 HSMA_TX_D_P5 LVDS or
2.5 V
P2
78 LVDS RX 5p or CMOS I/O data bit 25 ADB_D1 HSMA_RX_D_P5 LVDS or
2.5 V
U2
79 LVDS TX 5n or CMOS I/O data bit 26 ADA_D0 HSMA_TX_D_N5 LVDS or
2.5 V
P1
80 LVDS RX 5n or CMOS I/O data bit 27 ADB_D0 HSMA_RX_D_N5 LVDS or
2.5 V
U1
83 LVDS TX 6p or CMOS I/O data bit 28 ADA_OR HSMA_TX_D_P6 LVDS or
2.5 V
M4
84 LVDS RX 6p or CMOS I/O data bit 29 ADB_OR HSMA_RX_D_P6 LVDS or
2.5 V
U6
85 LVDS TX 6n or CMOS I/O data bit 30 ADA_OE HSMA_TX_D_N6 LVDS or
2.5 V
M3
86 LVDS RX 6n or CMOS I/O data bit 31 ADB_OE HSMA_RX_D_N6 LVDS or
2.5 V
U5
89 LVDS TX 7p or CMOS I/O data bit 32 ADA_SPI_CS HSMA_TX_D_P7 LVDS or
2.5 V
M2
90 LVDS RX 7p or CMOS I/O data bit 33 ADB_SPI_CS HSMA_RX_D_P7 LVDS or
2.5 V
R2
91 LVDS TX 7n or CMOS I/O data bit 34 AD_SDIO HSMA_TX_D_N7 LVDS or
2.5 V
M1
92 LVDS RX 7n or CMOS I/O data bit 35 AD_SCLK HSMA_RX_D_N7 LVDS or
2.5 V
R1
95 LVDS or CMOS clock out FPGA_CLK_A_P HSMA_CLK_OUT_P1 LVDS or
2.5 V
G6
Table A–1. HSMC Port A Interface Pin-Out Information (Part 2 of 4)
Data Conversion HSMC Schematic Development Board Schematic
Board
Reference
(J1) Description
Schematic
Signal Name
Schematic
Signal Name
I/O
Standard
Cyclone
III
Pin
Number