Altera Data Conversion HSMC - Manual (Page 40)

C–2 Appendix C: Pin-Out Information for the Cyclone III (3C25) Starter Board
Data Conversion HSMC Reference Manual © November 2008 Altera Corporation
83 A/D A Overrun to Host ADA_OR HSMC_TX_p6 2.5 V K2
84 A/D B Overrun to Host ADB_OR HSMC_RX_p6 2.5 V K5
85 A/D A Output Enable from
Host ADA_OE HSMC_TX_n6 2.5 V K1
86 A/D B Output Enable from
Host ADB_OE HSMC_RX_n6 2.5 V L5
89 A/D A SPI CS from Host ADA_SPI_CS HSMC_TX_p7 2.5 V L2
90 A/D B SPI CS from Host ADB_SPI_CS HSMC_RX_p7 2.5 V L4
91 Common A/D SDIO from Host AD_SDIO HSMC_TX_n7 2.5 V L1
92 Common A/D SCLK from
Host AD_SCLK HSMC_RX_n7 2.5 V L3
95 A/D Clock A from Host
Differential P FPGA_CLK_A_P HSMC_CLKOUT_p1 LVDS D14
96 External Clock from SMAs to
Host Differential P XT_IN_P HSMC_CLKIN_p1 LVDS F17
97 A/D Clock A from Host
Differential N FPGA_CLK_A_N HSMC_CLKOUT_n1 LVDS C14
98 External Clock from SMAs to
Host Differential N XT_IN_N HSMC_CLKIN_n1 LVDS F18
101 D/A A bit 13 from Host DA13 HSMC_TX_p8 2.5 V M2
102 D/A A bit 13 from Host DB13 HSMC_RX_p8 2.5 V P2
103 D/A A bit 12 from Host DA12 HSMC_TX_n8 2.5 V M1
104 D/A B bit 12 from Host DB12 HSMC_RX_n8 2.5 V P1
107 D/A A bit 11 from Host DA11 HSMC_TX_p9 2.5 V R2
108 D/A B bit 11 from Host DB11 HSMC_RX_p9 2.5 V T3
109 D/A A bit 10 from Host DA10 HSMC_TX_n9 2.5 V R1
110 D/A B bit 10 from Host DB10 HSMC_RX_n9 2.5 V R3
113 D/A A bit 9 from Host DA9 HSMC_TX_p10 2.5 V E17
114 D/A B bit 9 from Host DB9 HSMC_RX_p10 2.5 V G17
115 D/A A bit 8 from Host DA8 HSMC_TX_n10 2.5 V E18
116 D/A B bit 8 from Host DB8 HSMC_RX_n10 2.5 V G18
119 D/A A bit 7 from Host DA7 HSMC_TX_p11 2.5 V H17
120 D/A B bit 7 from Host DB7 HSMC_RX_p11 2.5 V K18
121 D/A A bit 6 from Host DA6 HSMC_TX_n11 2.5 V H18
122 D/A B bit 6 from Host DB6 HSMC_RX_n11 2.5 V L18
125 D/A A bit 5 from Host DA5 HSMC_TX_p12 2.5 V L17
126 D/A B bit 5 from Host DB5 HSMC_RX_p12 2.5 V L16
127 D/A A bit 4 from Host DA4 HSMC_TX_n12 2.5 V M18
128 D/A B bit 4 from Host DB4 HSMC_RX_n12 2.5 V M17
Table C–1. HSMC Port Interface Pin-Out Information (Part 2 of 3)
Data Conversion HSMC Schematic Development Board Schematic
Board
Reference
(J1) Description
Schematic
Signal Name
Schematic
Signal Name
I/O
Standard
Cyclone III
Pin Number