Mds system interface, i/o – Zilog Z8F0411 User Manual

Page 38

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background image

UM016905-1207

Schematics

MDS General-Purpose Board Development Kit

User Manual

27

Figure 18. MDS-GP Board Schematic (3 of 8)

5

5

4

4

3

3

2

2

1

1

D

D

C

C

B

B

A

A

ZDI INTERFACE

DIS_FL

F L _ W E

OFFBOARD

MDS System interface, I/O

NC

NC
NC

NC
NC
NC
NC

NC

NC

DO NOT POPULATE R15 and R18

IF R15 and R18 ARE POPULATED R29 AND R30 MUST BE REMOVED

96C0943-001

B

MDS General Purpose Platform

ZiLOG, Inc.

532 Race Street
San Jose, CA 95126

B

3

8

Thursday, March 25, 2004

Title

Size

Document Number

Rev

Date:

Sheet

of

A23

DB5

VCC_33V

DB0

PA2

-BUSREQ

A10

PC5

A17

A19

-RD

-WR

GND

A 5

PD5

D4

PA6

PA3

GND

D6

-RST_5

DB6

-WAIT

D4

A 6

PA1

A20

DB6

TCK

PD3

-HALT_SLP

-NMI

A 1

DB1

VCC_33V

PA0

D0

DB3

-BUSACK

A 8

GND

D5

GND

PC6

IICSDA

PA4

D5

-MREQ

PD7

VCC_33V

D0

PB1

A 0

VCC_33V

A11

TDI

DB7

PB3

A18

PB0

A12

-EN_DISP

DB2

PD0

VCC_33V

D1

DB7

IICSDA

VCC_33V

GND

DB0

A22

PD2

GND

A 2

GND

A 9

-CS0

PA5

-RD

D1

GND

PB7

PC4

D6

VCC_33V

-CS2

D2

-F91_WE

DB3

A14

A15

A 0

-WR

PB4

GND

DB2

PD4

GND

PC7

PA7

PC2

A21

D2

PC0

-TRSTN

A13

PD6

-WR

-WAIT

-RST

A 7

GND

-IOREQ

-INSTRD

DB4

-CS1

PB5

DB1

D3

IICSCL

D7

EZ80CLK

A 4

DB5

PC3

PD1

IICSCL

D3

PB2

GND

VCC_33V

DB4

-EN_DISP

A 3

D7

PC1

A16

A0
A1

A3

A2

A6
A7

A5

A4

A15

A10

A13

A11
A12

A9

A8

A14

A18
A19

A17

A16

D 7

D 0
D 1
D 2
D 3

D 6

D 5

D 4

P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7

P C 0

P C 7

P C 6

P C 5

P C 4

P C 1
P C 2
P C 3

- R E S E T

P D 3

P D 0
P D 1

P B 1

P B 0

P B 5

P D 7

P B 7

P B 4

P B 6

P B 2
P B 3

P D 6

P D 5

P D 4

P D 2

P B 6

-DIS_IRDA

A20
A21
A22
A23

-DIS_FLASH

T C K

T V C C _ R E S E T n

T R I G O U T

T D O

TDI

V C C _ 3 3 V

T M S

G N D

G N D

GND

G N D

-CS3

GND

G N D

V C C _ 3 3 V

G N D

TDI

T R I G O U T

T M S

T D O

T C K

V C C _ 3 3 V

-RST

P R S T n

V C C _ 5 V

V C C _ 5 V

V C C _ 5 V

V C C _ 5 V

V C C _ 3 3 V

JP1

C O N 3 0 X 2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

J11

H E A D E R 3 X 2

2
4
6

1
3
5

U 7 F

7 4 L V C 0 4 / S O

13

12

14

7

U 1 1 D

TC74LVT125

12

11

14

13

7

R16 10K

J6

1
2

P1

con 7x2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

R66
10K

C12
C A P _ N P

J10

I 2 C _ C O N

1
2
3
4

1
2
3
4

J7

H E A D E R 1 0 X 2

1
3
5
7
9

11
13
15
17
19

2
4
6
8
10
12
14
16
18
20

R17

10K

U 1 1 A

TC74LVT125

2

3

14

1

7

J8
- D A C K _ E N

1
2

R14

10K

JP2

C O N 3 0 X 2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

R13

10K

J9

1
2

R15
4.7K

U 9

74ACT245

2
3
4
5
6
7
8
9

19

1

18
17
16
15
14
13
12
11

20

10

A0
A1
A2
A3
A4
A5
A6
A7

O E

DIR

B0
B1
B2
B3
B4
B5
B6
B7

VCC

GND

U 1 2 A

TC74LVC08

1

2

3

14

7

S1

- R E S E T

1

3

R18
4.7K

A[0:23]

D[0:7]

- W R

-CS2

PA[0:7]

PC[0:7]

-RD

PD[0:7]

PB[0:7]

-EN_DISP

I2CSDA

I2CSCL

-IRDA_EN

-DIS_FLASH

-CS0

-CS3

-RST_5

-RST

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