Zilog EZ80190 - Manual (Page 79)

eZ80190 Development Kit
User Manual
General Array Logic Equations UM014108-0810
75
A1, //A17
A0, //A16
nCS2,
nEX_FL_DIS, // disables Flash on the expansion
// module, when Low
nEM_EN, // enables Development Platform LED
// and the general-purpose port.
nDIS_FL, // disables Module Flash when Low
nL_RD, // enables local data bus to be read
// by CPU
nmemen1,
nmemen2,
nmemen3,
nmemen4
);
input
nFL_DIS /* synthesis loc="P4"*/,
nCS0 /* synthesis loc="P5"*/,
nCS2 /* synthesis loc="P3"*/, //was 23
A7 /* synthesis loc="P6"*/,
A6 /* synthesis loc="P7"*/,
A5 /* synthesis loc="P9"*/,
A4 /* synthesis loc="P10"*/,
A3 /* synthesis loc="P11"*/,
A2 /* synthesis loc="P12"*/,
A1 /* synthesis loc="P13"*/,
A0 /* synthesis loc="P16"*/,
nEX_FL_DIS /* synthesis loc="P2"*/;