Zilog EZ80190 - Manual (Page 83)

eZ80190 Development Kit
User Manual
General Array Logic Equations UM014108-0810
79
nAN_WR,
nCT_WR,
nDIS_ETH
);
input nDIS_EM /* synthesis loc="P3"*/,
nEM_EN /* synthesis loc="P4"*/,
A0 /* synthesis loc="P5"*/,
A1 /* synthesis loc="P6"*/,
A2 /* synthesis loc="P10"*/,
A3 /* synthesis loc="P11"*/,
A4 /* synthesis loc="P12"*/,
A5 /* synthesis loc="P13"*/,
A6 /* synthesis loc="P27"*/,
A7 /* synthesis loc="P26"*/,
nIORQ /* synthesis loc="P2"*/,
nRD /* synthesis loc="P7"*/,
nCS /* synthesis loc="P25"*/, //CS3 for CS9800
nWR /* synthesis loc="P9"*/,
nMEMRQ /* synthesis loc="P16"*/;
output
nEM_RD /* synthesis loc="P17"*/,
nEM_WR /* synthesis loc="P18"*/,
nCT_WR /* synthesis loc="P19"*/,
nAN_WR /* synthesis loc="P20"*/,
nDIS_ETH /* synthesis loc="P21"*/;
parameter anode=8'h00;
parameter cathode=8'h01;