Zilog eZ80F92 - Manual (Page 36)

eZ80F92 Development Kit
User Manual
eZ80Acclaim!
®
Development Platform UM013911-0607
32
2. U18, address range
A80000h
–
AFFFFFh
3. U17, address range
A00000h
–
A7FFFFh
If SRAM memory is installed in a different order than the above
sequence, SRAM will not be contiguous unless the user is able to change
the address decoder, U10. Memory access decoding is performed by this
address decoder, implemented in the Generic Array Logic device,
GAL22LV10D (U10).
On-Chip SRAM
The eZ80F92 device on the eZ80F92 Flash Module contains 8 KB of on-
chip SRAM. Upon power-up, this SRAM is enabled and mapped to the
top 8 KB of memory address space. Using the RAM Address Register,
this 8 KB memory can be mapped to the top of any 64 KB block. It can
also be disabled. Please see the eZ80F92/eZ80F92 Product Specification
(PS0153) for more information.
Flash Memory
The eZ80F92 Development Kit allows off-chip Flash memories between
1 MB and 4 MB. This Flash memory is entirely located on the eZ80F92
Flash Module (in footprint only; as shipped from the factory, external
Flash is not installed).
Memory Map
A memory map of the eZ80
® CPU is illustrated in Figure 10. Flash mem-
ory and SRAM on the eZ80F92 Flash Module are addressed when CS0
and CS1 are active Low. SRAM on the eZ80Acclaim!
® Development
Platform is addressed when CS2 is active Low.
The location of on-chip SRAM is programmable by setting the RAM
address upper byte register. The upper 8 KB of any 64 KB memory page
can be selected. Addresses to enabled on-chip memories assume priority
over all chip selects. Please refer to the eZ80F92/eZ80F92 Product Speci-
fication (PS0153) for more details.