Zilog eZ80F92 - Manual (Page 56)

eZ80F92 Development Kit
User Manual
eZ80F92 Flash Module UM013911-0607
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enables received data to pass into the UART0 Receive FIFO data buffer.
Bit 2 is a test function that provides a loopback sequence from the TxD
pin to the RxD input.
Bit 1, the Receive Enable bit, is used to block data from filling up the
Receive FIFO when the eZ80F92 Flash Module is transmitting data.
Because IrDA data passes through the air as a light source, transmitted
data can also be received. This Receive Enable bit prevents this data from
being received. After the eZ80F92 Flash Module completes transmitting,
this bit is changed to allow for incoming messages.
The code that follows provides an example of how this function is
enabled on the eZ80F92 Flash Module.
//Init_IRDA
// Ensure to first set PD2 as a port bit, an output and set it
Low.
PD_ALT1 &= 0xFC; // PD0 = uart0tx, PD1 = uart0_rx
PD_ALT2 |= 0x03; // Enable alternate function
UART_LCTL0= 0x80; // Select dlab to access baud rate
generator
BRG_DLRL0=0x2F; // Baud rate Masterclock/(16*baudrate)
BRG_DLRH0=0x00; // High byte of baud rate
UART_LCTL0=0x00; // Disable dlab
UART_FCTL0=0xC7; // Clear tx fifo, enable fifo
UART_LCTL0=0x03; // 8bit, N, 1 stop
IR_CTL = 0x03; // enable IRDA Encode/decode and Receive
// enable bit.
//IRDA_Xmit
IR_CTL = 0x01; //Disable receive
Putchar(0xb0); //Output a byte to the uart0 port.